Datasheet > S2048A

S2048A

更新时间： 2024-09-16 19:50:43

品牌	Logo	应用领域
AMCC		电信电信集成电路
页数	文件大小	规格书
23页	172K
描述
Telecom Circuit, 1-Func, PQFP52, 10 X 10 MM, PLASTIC, QFP-52

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技术参数
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S2048A 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	QFP, QFP52,.52SQ	针数：	52
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.83	JESD-30 代码：	S-PQFP-G52
长度：	10 mm	功能数量：	1
端子数量：	52	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装等效代码：	QFP52,.52SQ
封装形状：	SQUARE	封装形式：	FLATPACK
电源：	3.3/5 V	认证状态：	Not Qualified
座面最大高度：	2.45 mm	子类别：	Other Telecom ICs
最大压摆率：	160 mA	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	TELECOM CIRCUIT
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
宽度：	10 mm	Base Number Matches：	1

S2048A 数据手册

DEVICE

SPECIFICATION

S2042/S2048

HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS

BiCMOS PECL CLOCK GENERATOR

HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS

GENERAL DESCRIPTION

FEATURES

• Functionally compliant with ANSI X3T11 Fibre

Channel physical and transmission protocol

standards

• S2042 transmitter incorporates phase-locked loop

(PLL) providing clock synthesis from low-speed

reference

The S2042 and S2048 transmitter and receiver pair

are designed to perform high-speed serial data trans-

mission over fiber optic or coaxial cable interfaces

conforming to the requirements of the ANSI X3T11

Fibre Channel specification. The chipset is select-

able to 1062.5, 531.25 or 265.625 Mbps data rates

with associated 10- or 20-bit data word.

• S2048 receiver PLL configured for clock and

data recovery

The chipset performs parallel-to-serial and serial-to-

parallel conversion and framing for block-encoded

data. The S2042 on-chip PLL synthesizes the high-

speed clock from a low-speed reference. The S2048

on-chip PLL synchronizes directly to incoming digital

signals to receive the data stream. The transmitter

and receiver each support differential PECL-compat-

ible I/O for fiber optic component interfaces, to

minimize crosstalk and maximize data integrity. Lo-

cal loopback allows for system diagnostics.

• 1062.5, 531.25 and 265.625 Mbps operation

• 10- or 20-bit parallel TTL compatible interface

• +3.3 V/+5 V power supply

• Low-jitter serial PECL compatible interface

• Lock detect

• Local loopback

• 10mm x 10mm 52 PQFP package

• Fibre Channel framing performed by receiver

• Continuous downstream clocking from receiver

• TTL compatible outputs

Figure 1 shows a typical network configuration incor-

porating the chipset.

APPLICATIONS

High-speed data communications

• Supercomputer/Mainframe

• Workstation

• Switched networks

• Proprietary extended backplanes

• Mass storage devices/RAID drives

Figure 1. System Block Diagram

Optical

S2048

S2042

Optical

Fibre

Channel

Controller

Fibre

Channel

Controller

S2042

Optical

S2048

Optical

April 10, 2000 / Revision B

12 3 4 5 6 7...23

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与S2048A相关器件

型号	品牌	获取价格	描述	数据表
S2048A10	AMCC	获取价格	Telecom Circuit, 1-Func, PQFP52, 10 X 10 MM, PLASTIC, QFP-52
S204R	MINMAX	获取价格	2W, Low Cost DIP, Single & Dual Output DC/DC Converters
S-2050	NIDEC	获取价格	ROTARY SELECTOR SWITCHES
S2050A	AMCC	获取价格	Ethernet Transceiver, PQFP52, 10 X 10 MM, COMPACT, PLASTIC, QFP-52
S2050A	ROCHESTER	获取价格	Ethernet Transceiver, PQFP52, 10 X 10 MM, COMPACT, PLASTIC, QFP-52
S2050A/D	AMCC	获取价格	Ethernet Transceiver, PQFP52, 10 X 10 MM, COMPACT, PLASTIC, QFP-52
S2050A/TD	AMCC	获取价格	Ethernet Transceiver, PQFP52, 10 X 10 MM, COMPACT, PLASTIC, QFP-52
S2050A-3	AMCC	获取价格	Ethernet Transceiver, PQFP52, 10 X 10 MM, COMPACT, PLASTIC, QFP-52
S2050A-3	ROCHESTER	获取价格	Ethernet Transceiver, PQFP52, 10 X 10 MM, COMPACT, PLASTIC, QFP-52
S2050A-3/D	AMCC	获取价格	Ethernet Transceiver, PQFP52, 10 X 10 MM, COMPACT, PLASTIC, QFP-52

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