RM7000C

更新时间： 2024-11-04 22:23:47

品牌	Logo	应用领域
PMC		微处理器
页数	文件大小	规格书
2页	37K
描述
64-Bit MIPS RISC Microprocessor with Integrated L2 Cache

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中文翻译

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数据手册

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RM7000C 数据手册

RM7000C

Preliminary

64-Bit MIPS RISC Microprocessor with Integrated L2 Cache

•

1600 Mbyte per-second peak

throughput

•

Fourteen fully prioritized vectored

interrupts-10 external, 2 internal, 2

software

FEATURES

• Dual-Issue symmetric superscalar

microprocessor

•

200 MHz max. freq., HSTL

multiplexed address/data bus

(SysAD200)

Specialized DSP integer Multiply-

Accumulate instructions

(MAD/MADU), and three-operand

Multiply instruction (MUL)

•

600MHz max CPU frequency

•

Capable of issuing two instructions

per clock cycle

•

Supports two outstanding reads with

out-of-order return

• Integrated primary and secondary

caches

•

I and D Test/Break-point (Watch)

registers for emulation and debug

• High-performance floating-point unit

•

1200 MFLOPS maximum

•

16KB Instruction, 16KB Data, and

256KB on-chip secondary

Performance counter for system

and software tuning and debug

•

IEEE754 compliant single and

double precision floating-point

operations

All are 4-way set associative with

32-byte line size

• 64-bit MIPS instruction set architecture

PACKAGING

Per-line locking in primary and

secondary caches

•

Data PREFETCH instruction allows

the processor to overlap cache miss

latency and instruction execution

•

Fully Static 0.13µ CMOS design

with dynamic power down logic

Fast Packet Cache™ increases

system efficiency in networking

applications

•

304 pin TBGA package, 31x31 mm

•

Single-cycle floating-point multiply-

add

• Integrated external cache controller

DEVELOPMENT TOOLS

• Integrated memory management unit

•

Allows up to 64Mbyte of external

cache for applications with large

data sets

•

Fully associative TLB

• Operating Systems:

•

64/48 dual entries map 128/96

pages

•

Linux by MontaVista and Red Hat

VxWorks by Wind River Systems

Nucleus by Accelerated Technology

Neutrino by QNX Software Systems

•

Enhanced protocol eliminates

requirement for TAG RAMS

•

Variable page size

• Embedded application enhancements

• High-performance system interface

• Compiler Suites

BLOCK DIAGRAM

64-bit Integer Unit

Dual-Issue Superscalar

System Control

PC Unit

64-bit FP Unit

Double/Single IEEE754

Integer Multiplier

Instr. Dispatch

I-Cache

16KB, 4-way, lockable

MMU

Fully Assoc., 48 or 64 Entry

D-Cache

16KB, 4-way, lockable

System Cache (L2)

256KB, 4-way, lockable

Bus Interface Unit

L3 Cache Control

Int Ctlr

SysA /D Bus & L3 Ctr

NMI, INT9 – INT0

PMC- 2011604(P1)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

中文翻译

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