Datasheet > RM7000C-533T

RM7000C-533T

更新时间： 2024-11-05 21:12:43

品牌	Logo	应用领域
PMC		/
页数	文件大小	规格书
2页	41K
描述
Microprocessor,

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

RM7000C-533T 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
Reach Compliance Code：	compliant	风险等级：	5.81
湿度敏感等级：	3	Base Number Matches：	1

RM7000C-533T 数据手册

RM7000C™

64-Bit MIPS RISC Microprocessor with Integrated L2 Cache

•

Fast Packet Cache™ increases

system efficiency in networking

applications

• Integrated memory management unit

FEATURES

•

Fully associative joint TLB (shared

by I and D translations)

• Dual issue symmetric superscalar

microprocessor with instruction

prefetch optimized for system level

price/performance

• Integrated external cache controller

(up to 64 MB)

64/48 dual entries map 128/96

pages

•

User-selectable EZ Cache protocol

eliminates the need for external tag

RAMs.

Variable page size

•

533, 600 MHz operating frequency

• Embedded application enhancements

•

>1080 Dhrystone 2.1 MIPS @ 600

MHz

•

Specialized DSP integer Multiply-

Accumulate instructions,

• High-performance floating-point unit -

1600 MFLOPS maximum

• High-performance system interface

(MAD/MADU) and three-operand

multiply instruction (MUL)

•

1280 MB per second peak

throughput

•

Single cycle repeat rate for common

single-precision operations and

some double-precision operations

•

I&D Test/Break-point (Watch)

registers for emulation & debug

200 MHz maximum frequency using

HSTL signaling on the SysAD bus

Single cycle repeat rate for single-

precision combined multiply-add

operations

Performance counter for system

and software tuning & debug

Multiplexed address/data bus

(SysAD) supports 1.5 V, 2.5 V, 3.3

V I/O logic

Fourteen fully prioritized vectored

interrupts - 10 external, 2 internal, 2

software

Two cycle repeat rate for double-

precision multiply and double-

precision combined multiply-add

operations

•

Processor clock multipliers 2, 2.5, 3,

3.5, 4, 4.5, 5, 6, 7, 8, 9

• Fully static CMOS design with dynamic

power down logic

• Pin compatible with RM5271, RM7000,

RM7000A and RM7000B in 304-pin

TBGA package, 31x31 mm

• Integrated primary and secondary

caches

• MIPS IV superset instruction set

architecture

•

All are 4-way set associative with

32-byte line size

•

Data PREFETCH instruction allows

the processor to overlap cache miss

latency and instruction execution

16 KB instruction, 16 KB data, 256

KB on-chip secondary

Per line cache locking in primaries

and secondary

•

Single-cycle floating-point multiply-

add

BLOCK DIAGRAM

64-bit Integer Unit

Dual-Issue Superscalar

System Control

PC Unit

64-bit FP Unit

Double/Single IEEE754

Integer Multiplier

Instr. Dispatch

I-Cache

MMU

D-Cache

16KB, 4-way, lockable

Fully Assoc., 48 or 64 Entry

16KB, 4-way, lockable

System Cache (L2)

256KB, 4-way, lockable

Bus Interface Unit

L3 Cache Control

Int Ctlr

64-bit

SysA /D Bus & L3 Ctr

NMI, INT9 – INT0

PMC- 2011604 (R3)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

中文翻译

下载PDF

与RM7000C-533T相关器件

型号	品牌	获取价格	描述	数据表
RM7000C-600T	MICROSEMI	获取价格	Microprocessor,
RM700B	EDI	获取价格	HIGH VOLTAGE HIGH CURRENT MINIATURE RECTIFIERS
RM702024	TE	获取价格	Power Relay
RM702524	TE	获取价格	Power Relay
RM702615	TE	获取价格	Power Relay
RM702730	TE	获取价格	Power Relay
RM703024	TE	获取价格	Power Relay
RM703524	TE	获取价格	Power Relay
RM7035C	PMC	获取价格	Microprocessor,
RM703615	TE	获取价格	Power Relay

与RM7000C-533T相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

13
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

9
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

35
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

31

产品中心

服务支持

精选活动

关于我们

帮助中心

RM7000C-533T

RM7000C-533T 技术参数

RM7000C-533T 数据手册

与RM7000C-533T相关器件

与RM7000C-533T相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

RM7000C-533T

RM7000C-533T 技术参数

RM7000C-533T 数据手册

与RM7000C-533T相关器件

与RM7000C-533T相关文章

您还可以找

您在本页遇到什么问题？