Datasheet > RM7000C-600T

RM7000C-600T

更新时间： 2024-11-05 21:10:15

品牌	Logo	应用领域
美高森美 - MICROSEMI		/
页数	文件大小	规格书
2页	38K
描述
Microprocessor,

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中文翻译

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技术参数
数据手册

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RM7000C-600T 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	compliant	风险等级：	5.82
Base Number Matches：	1

RM7000C-600T 数据手册

RM7000C

Released

64-Bit MIPS RISC Microprocessor with Integrated L2 Cache

•

16 Kbytes instruction, 16 Kbytes

data, 256 Kbytes on-chip

secondary.

• MIPS IV superset instruction set

architecture:

FEATURES

• Dual issue symmetric superscalar

microprocessor with instruction

prefetch optimized for system level

price/performance:

•

Data PREFETCH instruction allows

the processor to overlap cache miss

latency and instruction execution.

•

Per line cache locking in primaries

and secondary.

Fast Packet Cache increases

system efficiency in networking

applications.

•

Single-cycle floating-point multiply-

add.

•

533, 600 MHz operating frequency.

•

>1380 Dhrystone 2.1 MIPS @

600 MHz.

• Integrated memory management unit:

• Integrated external cache controller

(up to 64 Mbytes).

• High-performance floating-point unit -

1600 MFLOPS maximum:

•

Fully associative joint TLB (shared

by I and D translations).

• High-performance system interface:

•

1600 Mbyte/s peak throughput.

64/48 dual entries map 128/96

pages.

•

200 MHz maximum frequency using

HSTL signaling on the SysAD bus.

•

Single cycle repeat rate for common

single-precision operations and

some double-precision operations.

Variable page size.

•

Multiplexed address/data bus

(SysAD) supports 1.5 V, 2.5 V,

3.3 V I/O logic.

• Embedded application enhancements:

•

Specialized DSP integer Multiply-

Accumulate instructions,

Single cycle repeat rate for single-

precision combined multiply-add

operations.

Processor clock multipliers 2, 2.5, 3,

3.5, 4, 4.5, 5, 6, 7, 8, 9.

(MAD/MADU) and three-operand

multiply instruction (MUL).

• Integrated primary and secondary

caches:

Two cycle repeat rate for double-

precision multiply and double-

precision combined multiply-add

operations.

•

I&D Test/Break-point (Watch)

registers for emulation & debug.

•

All are 4-way set associative with

32-byte line size.

Performance counter for system

and software tuning & debug.

14 fully prioritized vectored

interrupts - 10 external, 2 internal,

2 software.

BLOCK DIAGRAM

64-bit Integer Unit

64-bit Floating-Point Unit

Double / Single

IEEE 754

System Control

PC Unit

Dual-Issue

Superscalar

Integer Multiplier

Instruction Dispatch

Memory Management Unit

Fully Associative

Instruction Cache

16 KB, 4-way, lockable

Data Cache

16 KB, 4-way, lockable

48 or 64 Entry

System Cache (L2)

256 KB, 4-way, lockable

Bus Interface Unit

L3 Cache Control

Interrupt Controller

NMI, INT9 – INT0

SysAD Bus & L3 Controller

PMC-2011604

Issue 5

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC.,

AND FOR ITS CUSTOMERS’ INTERNAL USE

中文翻译

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