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RM7065 PDF预览

RM7065

更新时间: 2024-11-04 22:23:47
品牌 Logo 应用领域
PMC 微处理器
页数 文件大小 规格书
2页 36K
描述
64-Bit MIPS RISC Microprocessor with Integrated L2 Cache

RM7065 数据手册

 浏览型号RM7065的Datasheet PDF文件第2页 
RM7065A  
64-Bit MIPS RISC Microprocessor with Integrated L2 Cache  
Supports two outstanding reads with  
out-of-order return  
Performance counter for system  
and software tuning and debug  
FEATURES  
• Dual-issue symmetric superscalar  
microprocessor  
• High-performance floating-point unit  
Fourteen fully prioritized vectored  
interrupts-10 external, 2 internal, 2  
software  
800 MFLOPS maximum  
400 MHz max CPU frequency  
IEEE754 compliant single and  
double precision floating-point  
operations  
300 MHz max CPU frequency at I-  
temp (-40-85 C)  
PACKAGING  
• Fully Static 0.18µ CMOS design with  
dynamic power down logic  
Capable of issuing two instructions  
per clock cycle  
• 64-bit MIPS instruction set architecture  
Data PREFETCH instruction allows  
the processor to overlap cache miss  
latency and instruction execution  
• Integrated primary and secondary  
caches  
• 256 pin TBGA package, 27x27 mm  
16KB instruction, 16KB Data, and  
256KB on-chip secondary  
Single-cycle floating-point multiply-  
add  
All are 4-way set associative with  
32-byte line size  
DEVELOPMENT TOOLS  
• Integrated memory management unit  
Fully associative TLB  
• Operating Systems:  
Per-line locking in primary and  
secondary caches  
64/48 dual entries map 128/96  
pages  
Linux by MontaVista and Red Hat  
VxWorks by Wind River Systems  
Nucleus by Accelerated Technology  
Neutrino by QNX Software Systems  
Fast Packet Cache™ increases  
system efficiency in networking  
applications  
Variable page size  
• Embedded application enhancements  
Specialized DSP integer Multiply-  
Accumulate instructions  
(MAD/MADU), and three-operand  
Multiply instruction (MUL)  
• High-performance system interface  
• Compiler Suites  
1000 Mbyte per-second peak  
throughput  
Algorithmics  
Green Hills Software  
Red Hat  
125 MHz maximum frequency  
multiplexed address/data bus  
(SysAD)  
I and D Test/Break-point (Watch)  
registers for emulation and debug  
BLOCK DIAGRAM  
64-bit Integer Unit  
Dual-Issue Superscalar  
64-bit FP Unit  
Double/Single IEEE754  
System Control  
PC Unit  
Integer Multiplier  
Instr. Dispatch  
I-Cache  
MMU  
D-Cache  
16KB, 4-way, lockable  
Fully Assoc., 48 or 64 Entry  
16KB, 4-way, lockable  
System Cache (L2)  
256KB, 4-way, lockable  
Bus Interface Unit  
Int Ctlr  
64-bit  
SysA /D Bus  
NMI, INT9 – INT0  
PMC- 2011599 (R2)  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
© Copyright PMC-Sierra, Inc. 2001  

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