Datasheet > RM7035C

RM7035C

更新时间： 2024-11-05 17:55:07

品牌	Logo	应用领域
PMC		/
页数	文件大小	规格书
2页	88K
描述
Microprocessor,

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中文翻译

获取价格

技术参数
数据手册

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RM7035C 技术参数

生命周期：	Transferred	Reach Compliance Code：	unknown
风险等级：	5.8	Base Number Matches：	1

RM7035C 数据手册

RM7035C/RM7065C

Microprocessors

Preliminary

64-Bit MIPS RISC Microprocessors with Integrated L2 Cache

•

16 Kbytes instruction, 16 Kbytes

data, 256 Kbytes on-chip

secondary.

•

Single-cycle floating-point multiply-

add.

FEATURES

• Dual issue symmetric superscalar

microprocessor with instruction

prefetch optimized for system level

price/performance:

• Integrated memory management unit:

•

Per line cache locking in primaries

and secondary.

•

Fully associative joint TLB (shared

by I and D translations).

Fast Packet Cache™ increases

system efficiency in networking

applications.

64/48 dual entries map 128/96

pages.

•

466, 533, 600 MHz operating

frequency.

Variable page size.

•

>1380 Dhrystone 2.1 MIPS @

600 MHz.

• High-performance floating-point unit -

1600 MFLOPS maximum:

• Embedded application enhancements:

•

Specialized DSP integer Multiply-

Accumulate instructions,

(MAD/MADU) and three-operand

multiply instruction (MUL).

• High-performance system interface:

•

Single cycle repeat rate for common

single-precision operations and

some double-precision operations.

•

1600 Mbyte/s peak throughput.

•

200 MHz maximum frequency using

HSTL signaling on the SysAD bus.

Single cycle repeat rate for single-

precision combined multiply-add

operations.

•

I&D Test/Break-point (Watch)

registers for emulation & debug.

•

Multiplexed address/data (SysAD)

bus supports 1.5 V, 2.5 V, 3.3 V I/O

logic.

Performance counter for system

and software tuning & debug.

Two cycle repeat rate for double-

precision multiply and double-

precision combined multiply-add

operations.

•

Processor clock multipliers 2, 2.5, 3,

3.5, 4, 4.5, 5, 6, 7, 8, 9.

14 fully prioritized vectored

interrupts - 10 external, 2 internal, 2

software.

Support for 64- or 32-bit interfaces.

• Integrated primary and secondary

caches:

• MIPS IV superset instruction set

architecture:

•

All are 4-way set associative with

32-byte line size.

•

Data PREFETCH instruction allows

the processor to overlap cache miss

latency and instruction execution.

Integrated External External Bus

CPU Frequency

VccInt VccIO

Device

I/D Cache

L2 Cache

Support

Bus

Width

Frequency

(MHz)

Package

(MHz)

(V)

RM7035C

RM7065C

466,533,600

16KB/16KB

256 KB

32-bit

64-bit

200

1.3

2.5/3.3 128-ExposedPad™

2.5/3.3

256-TBGA or

216-ExposedPad™

BLOCK DIAGRAM

64-bit Integer Unit

Dual-Issue

64-bit Floating-Point Unit

Double / Single

IEEE 754

System Control

PC Unit

Superscalar

Integer Multiplier

Instruction Dispatch

Memory Management Unit

Fully Associative

Instruction Cache

16 KB, 4-way, lockable

Data Cache

16 KB, 4-way, lockable

48 or 64 Entry

System Cache (L2)

256 KB, 4-way, lockable

Bus Interface Unit

Interrupt Controller

NMI, INT9 – INT0

32-bit (RM7035C)

32/64-bit (RM7065C)

SysAD Bus

PMC-2020578

Issue 2

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC.,

AND FOR ITS CUSTOMERS’ INTERNAL USE

中文翻译

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与RM7035C相关器件

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RM703615	TE	获取价格	Power Relay
RM703730	TE	获取价格	Power Relay
RM705024	TE	获取价格	Power Relay
RM705524	TE	获取价格	Power Relay
RM705615	TE	获取价格	Power Relay
RM705730	TE	获取价格	Power Relay
RM7065	PMC	获取价格	64-Bit MIPS RISC Microprocessor with Integrated L2 Cache
RM7065A	PMC	获取价格	64-Bit MIPS RISC Microprocessor with Integrated L2 Cache
RM7065C	PMC	获取价格	暂无描述
RM7065C-466L-D004	PMC	获取价格	暂无描述

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