Datasheet > Q67100-Q2018

Q67100-Q2018

更新时间： 2024-09-16 23:06:07

品牌	Logo	应用领域
英飞凌 - INFINEON		/
页数	文件大小	规格书
10页	81K
描述
2M x 32-Bit Dynamic RAM Module

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中文翻译

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数据手册

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Q67100-Q2018 数据手册

2M x 32-Bit Dynamic RAM Module

HYM 322030S/GS-50/-60/-70

Advanced Information

• 2 097 152 words by 32-bit organization

• 1 memory bank

• Fast access and cycle time

50 ns access time

90 ns cycle time (-50 version)

60 ns access time

110 ns cycle time (-60 version)

70 ns access time

130 ns cycle time (-70 version)

• Fast page mode capability

35 ns cycle time (-50 version)

40 ns cycle time (-60 version)

45 ns cycle time (-70 version)

• Single + 5 V (± 10 %) supply

• Low power dissipation

max. 2640 mW active (-50 version)

max. 2420 mW active (-60 version)

max. 2200 mW active (-70 version)

CMOS – 22 mW standby

TTL

–44 mW standby

• CAS-before-RAS refresh

RAS-only-refresh

Hidden-refresh

• 4 decoupling capacitors mounted on substrate

• All inputs, outputs and clocks fully TTL compatible

• 72 pin Single in-Line Memory Module (L-SIM-72-9 ) with 20.32 mm (800 mil) height

• Utilizes four 2M × 8 -DRAMs in 400 mil SOJ packages

• 2048 refresh cycles / 32 ms with 11/10 addressing

• Optimized for use in byte-write non-parity applications

• Tin-Lead contact pads (S-version)

• Gold contact pads (GS - version)

Semicounductor Group

9.95

12 3 4 5 6 7...10

中文翻译

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