Datasheet > PUMD3/A2,115

PUMD3/A2,115

更新时间： 2023-01-02 16:53:29

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
11页	306K
描述
PRE-BIASED "DIGITAL" TRANSISTOR,50V V(BR)CEO,SOT-363

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数据手册

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PUMD3/A2,115 数据手册

PEMD3; PIMD3; PUMD3

NPN/PNP resistor-equipped transistors;

R1 = 10 kΩ, R2 = 10 kΩ

Rev. 10 — 15 November 2009

Product data sheet

1. Product profile

1.1 General description

NPN/PNP Resistor-Equipped Transistors (RET).

Table 1. Product overview

Type number

Package

NXP

PNP/PNP

complement

NPN/NPN

complement

JEITA

PEMD3

PIMD3

PUMD3

SOT666

SOT457

SOT363

PEMB11

PEMH11

SC-74

SC-88

PUMB11

PUMH11

1.2 Features

Built-in bias resistors

Simplifies circuit design

Reduces component count

Reduces pick and place costs

1.3 Applications

Low current peripheral driver

Control of IC inputs

Replaces general-purpose transistors in digital applications

1.4 Quick reference data

Table 2.

Symbol

V_CEO

I_O

Quick reference data

Parameter

Conditions

Min

Typ

Max

Unit

collector-emitter voltage

output current (DC)

bias resistor 1 (input)

bias resistor ratio

open base

100

kΩ

R2/R1

0.8

1.2

12 3 4 5 6 7...11

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PUMD3/A2,165	NXP	获取价格	PRE-BIASED "DIGITAL" TRANSISTOR,50V V(BR)CEO,SOT-363
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PUMD30,115	NXP	获取价格	PEMD30; PUMD30 - NPN/PNP double resistor-equipped transistors; R1 = 2.2 kOhm, R2 = open TS
PUMD3-Q	NEXPERIA	获取价格	50 V, 100 mA NPN/PNP resistor-equipped double
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PUMD4	NXP	获取价格	Low VCEsat (BISS) transistors
PUMD4	NEXPERIA	获取价格	50 V, 100 mA NPN/PNP resistor-equipped double