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PO74G74ASIR PDF预览

PO74G74ASIR

更新时间: 2024-11-15 06:04:35
品牌 Logo 应用领域
POTATO 触发器
页数 文件大小 规格书
6页 560K
描述
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

PO74G74ASIR 数据手册

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PO54G74A, PO74G74A  
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS  
WITH CLEAR AND PRESET  
10/10/07  
54, 74 Series GHz Logic  
FEATURES:  
DESCRIPTION:  
. Patented technology  
. Specified From –40°C to 85°C, –40°C to 125°C,  
and –55°C to 125°C  
Potato Semiconductor’s PO74G74A is designed for  
world top performance using submicron CMOS  
technology to achieve higher than 600MHz TTL  
/CMOS output frequency with less than 2ns propaga-  
tion delay.  
This dual D flip-flop is designed for 1.65-V to 3.6-V  
VCC operation.  
. Operating frequency is faster than 600MHz  
. VCC Operates from 1.65V to 3.6V  
. Propagation delay < 2ns max with 15pf load  
. Low input capacitance: 4pf typical  
. Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
. ESD Protection Exceeds JESD 22  
. 5000-VHuman-BodyModel (A114-A)  
. 200-VMachineModel (A115-A)  
Inputs can be driven from either 3.3V or 5V devices.  
This feature allows the use of these devices as  
translators in a mixed 3.3V/5V system environment.  
. Available in 14pin 150mil wide SOIC package  
. Available in 14pin Ceramic Dual Flatpack  
. Available in 20pin Leadless Ceramic Chip Carrier  
Pin Configuration  
V
1CLR  
1D  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
CC  
2CLR  
2D  
3
2
1
20 19  
18  
1CLK  
NC  
2D  
4
5
6
7
8
1CLK  
17  
16  
15  
14  
NC  
2CLK  
2PRE  
2Q  
1PRE  
1Q  
1PRE  
NC  
2CLK  
NC  
1Q  
2PRE  
9 10 11 12 13  
1Q  
GND  
8
2Q  
Logic Block Diagram  
Pin Description  
INPUTS  
OUTPUTS  
Vcc  
2CLR  
14  
13  
PRE  
L
CLR  
H
CLK  
X
D
X
X
X
H
L
Q
H
L
Q
L
1
2
3
4
5
6
7
1CLR  
1D  
PRE  
D
Q
Q
H
L
X
H
1
L
L
X
H
H
L
H
12 2D  
1CLR  
1PRE  
1Q  
CLR  
H
H
L
2CLK  
11  
10  
9
H
H
H
PRE  
H
H
L
X
Q0  
Q 0  
2PRE  
2Q  
Q
Q
D
2
1Q  
CLR  
GND  
8
2Q  
1
Copyright © Potato Semiconductor Corporation  

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