Datasheet > PO74G74ASU

PO74G74ASU

更新时间： 2024-11-15 06:04:35

品牌	Logo	应用领域
POTATO		触发器
页数	文件大小	规格书
6页	560K
描述
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

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中文翻译

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数据手册

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PO74G74ASU 数据手册

PO54G74A, PO74G74A

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH CLEAR AND PRESET

10/10/07

54, 74 Series GHz Logic

FEATURES:

DESCRIPTION:

. Patented technology

. Specified From –40°C to 85°C, –40°C to 125°C,

and –55°C to 125°C

Potato Semiconductor’s PO74G74A is designed for

world top performance using submicron CMOS

technology to achieve higher than 600MHz TTL

/CMOS output frequency with less than 2ns propaga-

tion delay.

This dual D flip-flop is designed for 1.65-V to 3.6-V

VCC operation.

. Operating frequency is faster than 600MHz

. VCC Operates from 1.65V to 3.6V

. Propagation delay < 2ns max with 15pf load

. Low input capacitance: 4pf typical

. Latch-Up Performance Exceeds 250 mA Per

JESD 17

. ESD Protection Exceeds JESD 22

. 5000-VHuman-BodyModel (A114-A)

. 200-VMachineModel (A115-A)

Inputs can be driven from either 3.3V or 5V devices.

This feature allows the use of these devices as

translators in a mixed 3.3V/5V system environment.

. Available in 14pin 150mil wide SOIC package

. Available in 14pin Ceramic Dual Flatpack

. Available in 20pin Leadless Ceramic Chip Carrier

Pin Configuration

1CLR

2CLR

20 19

1CLK

2CLK

2PRE

1PRE

2CLK

2PRE

9 10 11 12 13

GND

Logic Block Diagram

Pin Description

INPUTS

OUTPUTS

Vcc

2CLR

PRE

CLR

CLK

1CLR

PRE

12 2D

1CLR

1PRE

CLR

↑

2CLK

↑

PRE

Q₀

Q ₀

2PRE

CLR

GND

12 3 4 5 6

中文翻译

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