Datasheet > PO74HSTL85353A_14

PO74HSTL85353A_14

更新时间： 2024-11-15 12:56:39

品牌	Logo	应用领域
POTATO		/
页数	文件大小	规格书
7页	1489K
描述
300MHz HSTL Potato Chip

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PO74HSTL85353A

www.potatosemi.com

LVCMOS and XTAL Input to HSTLOutput 1:4 Fanout Buffer

300MHz HSTL Potato Chip

DESCRIPTION:

FEATURES:

The PO74HSTL85353A is a low-skew, 1-to-4 differential

fanout buffer targeted to meet the requirements of

high-performance clock and data distribution applications.

The device is implemented on CMOS technology and has

a fully differential internal architecture that is optimized to

achieve low signal skews at operating frequencies of up to

300MHz .

. Patented Technology

. Four HSTL differential outputs

. Two single LVTTL/LVCMOS inputs

(selectable LVCMOS/ LVTTL clock or crystal input)

. Operating frequency up to 300MHz with 15pf load

. Very low output pin to pin skew < 50ps

. 3.4-ns propagation delay (max)

. 2.4V to 3.6V power supply

. Industrial temperature range: –40°C to 85°C

. 20-pin TSSOP package

The device features two inputs, one is LVTTL / LVCMO

signal and the other is crystal input. This mux is

controlled by the CLK_SEL pin. The PO74HSTL85353A

functions as a signal-level translator and fanout on

LVCMOS / LVTTL single-ended signal to four HSTL

differential loads. Since the PO74HSTL85353A

introduces negligible jitter to the timing budget, it is the

ideal choice for distributing high frequency, high precision

clocks across back-planes and boards in communication

systems.

Pin Configuration

Logic Block Diagram

VEE

CLK_EN

CLK_SEL

CLK

Pullup

CLK_EN

nQ0

V^CC

Pulldown

CLK

nQ0

nQ1

XTAL_IN

OSC

XTAL_IN

XTAL_OUT

nQ1

XTAL_OUT

CLK_SEL

nQ2

V^CC

Pulldown

nQ2

nQ3

V^CC

nQ3

Potato Semiconductor Corporation

01/01/10

12 3 4 5 6 7

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