Datasheet > PO74HSTL85352ASU

PO74HSTL85352ASU

更新时间： 2024-11-15 11:59:31

品牌	Logo	应用领域
POTATO		时钟
页数	文件大小	规格书
7页	1394K
描述
The PO74HSTL85352A is a low-skew, 1-to-2 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications.

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PO74HSTL85352ASU 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.8
Base Number Matches：	1

PO74HSTL85352ASU 数据手册

PO74HSTL85352A

www.potatosemi.com

LVCMOS Input to HSTL Output 1:2 Fanout Buffer

300MHz TTL/CMOS Potato Chip

DESCRIPTION:

FEATURES:

The PO74HSTL85352A is a low-skew, 1-to-2 differential

. Patented Technology

fanout buffer targeted to meet the requirements of

high-performance clock and data distribution applications.

The device is implemented on CMOS technology and has

a fully differential internal architecture that is optimized to

achieve low signal skews at operating frequencies of up to

300MHz .

. Two HSTL differential outputs

. Two single LVTTL/LVCMOS inputs

. Operating frequency up to 300MHz with 15 pf load

. Very low output pin to pin skew < 30ps

. 3.2-ns propagation delay (max)

. 2.4V to 3.6V power supply

. Industrial temperature range: –40°C to 85°C

. 14-pin TSSOP package

The device features two single-ended input paths that are

multiplexed internally. This mux is controlled by the

CLK_SEL pin. The PO74HSTL85352A functions as a

signal-level translator and fanout on LVCMOS / LVTTL

single-ended signal to two pair of HSTL differential loads.

Since the PO74HSTL85352A introduces negligible jitter

to the timing budget, it is the ideal choice for distributing

high frequency, high precision clocks across back-planes

and boards in communication systems.

Pin Configuration

Logic Block Diagram

VEE

V^CC

CLK_EN

nQ0

CLK_SEL

CLK0

CLK1

nQ0

nQ1

V^EE

CLK_SEL

nQ1

V^CC

CLK1

V^CC

Potato Semiconductor Corporation

01/01/10

12 3 4 5 6 7

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