Datasheet > PO74HSTL85350ATR

PO74HSTL85350ATR

更新时间： 2024-11-15 06:04:35

品牌	Logo	应用领域
POTATO		/
页数	文件大小	规格书
7页	567K
描述
LVCMOS Input to HSTL Output 1:4 Fanout Buffer

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PO74HSTL85350ATR 数据手册

PO74HSTL85350A

LVCMOS Input to HSTL Output 1:4 Fanout Buffer

03/24/07

300MHz HSTL Potato Chip

DESCRIPTION:

FEATURES:

The PO74HSTL85350A is a low-skew, 1-to-4 differential

fanout buffer targeted to meet the requirements of

high-performance clock and data distribution applications.

The device is implemented on CMOS technology and has

a fully differential internal architecture that is optimized to

achieve low signal skews at operating frequencies of up to

300MHz .

. Patented Technology

. Four HSTL differential outputs

. Two single LVTTL/LVCMOS inputs

. Operating frequency up to 300MHz with 15 pf load

. Very low output pin to pin skew < 50ps

. 3.4-ns propagation delay (max)

. 2.4V to 3.6V power supply

. Industrial temperature range: –40°C to 85°C

. 20-pin TSSOP package

The device features two single-ended input paths that are

multiplexed internally. This mux is controlled by the

CLK_SEL pin. The PO74HSTL85350A functions as a

signal-level translator and fanout on LVCMOS / LVTTL

single-ended signal to four HSTL differential loads. Since

the PO74HSTL85350A introduces negligible jitter to the

timing budget, it is the ideal choice for distributing high

frequency, high precision clocks across back-planes and

boards in communication systems.

Pin Configuration

Logic Block Diagram

VEE

CLK_EN

nQ0

V^CC

CLK_SEL

CLK0

CLK1

nQ0

nQ1

CLK1

nQ2

CLK_SEL

nQ2

V^CC

nQ3

V^CC

nQ3

12 3 4 5 6 7

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PO74HSTL85352A_14	POTATO	获取价格	LVCMOS Input to HSTL Output 1:2 Fanout Buffer
PO74HSTL85352ASR	POTATO	获取价格	The PO74HSTL85352A is a low-skew, 1-to-2 differential fanout buffer targeted to meet the r
PO74HSTL85352ASU	POTATO	获取价格	The PO74HSTL85352A is a low-skew, 1-to-2 differential fanout buffer targeted to meet the r
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