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PO74G38072ASR PDF预览

PO74G38072ASR

更新时间: 2024-11-15 06:04:35
品牌 Logo 应用领域
POTATO 时钟驱动器
页数 文件大小 规格书
5页 475K
描述
3.3V 1:2 CMOS Clock Driver

PO74G38072ASR 技术参数

生命周期:Contact Manufacturer包装说明:,
Reach Compliance Code:unknown风险等级:5.81
Base Number Matches:1

PO74G38072ASR 数据手册

 浏览型号PO74G38072ASR的Datasheet PDF文件第2页浏览型号PO74G38072ASR的Datasheet PDF文件第3页浏览型号PO74G38072ASR的Datasheet PDF文件第4页浏览型号PO74G38072ASR的Datasheet PDF文件第5页 
PO74G38072A  
3.3V 1:2 CMOS Clock Driver  
02/13/07  
1GHz TTL/CMOS Potato Chip  
FEATURES:  
DESCRIPTION:  
. Patented technology  
. Max input frequency > 1GHz  
. Operating frequency up to 1GHz with 2pf load  
. Operating frequency up to 700MHz with 5pf load  
Potato Semiconductor’s PO74G38072A is  
designed for world top performance using  
submicron CMOS technology to achieve 1GHz  
TTL output frequency with less than 20ps  
. Operating frequency up to 400MHz with 15pf load output pin to pin skew.  
. Operating frequency up to 200MHz with 50pf load  
PO74G38072A is a 3.3V CMOS 1 input to 2  
. Very low output pin to pin skew < 20ps  
outputs Buffered driver to achieve 1GHz output  
frequency. Typical applications are clock and  
signal distribution.  
. VCC = 1.65V to 3.6V  
. Propagation delay < 1.3ns max with 15pf load  
. Low input capacitance: 3pf typical  
. 1:2 fanout  
Inputs can be driven from either 3.3V or 5V devices.  
This feature allows the use of these devices as  
translators in a mixed 3.3V/5V system environment.  
. Available in 8 pin SOIC package  
Pin Configuration  
Logic Block Diagram  
1
8
7
GND  
V
CC  
O1  
2
3
4
VCC  
O
O
2
1
IN  
IN  
6
5
O2  
GND  
GND  
Pin Description  
Pin Name  
Description  
IN  
Input  
Ox  
Outputs  
1
Copyright © Potato Semiconductor Corporation  

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