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PO74G373ATU PDF预览

PO74G373ATU

更新时间: 2024-11-15 06:04:35
品牌 Logo 应用领域
POTATO 锁存器输出元件
页数 文件大小 规格书
6页 545K
描述
OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

PO74G373ATU 技术参数

生命周期:Contact Manufacturer包装说明:,
Reach Compliance Code:unknown风险等级:5.75
Base Number Matches:1

PO74G373ATU 数据手册

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PO54G373A, PO74G373A  
OCTAL TRANSPARENT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
10/22/07  
54, 74 Series GHz Logic  
FEATURES:  
DESCRIPTION:  
Potato Semiconductor’s PO74G373A is designed for  
world top performance using submicron CMOS  
. Patented technology  
. Operating frequency up to 1.125GHz with 2pf load  
. Operating frequency up to 700MHz with 5pf load  
. Operating frequency up to 350MHz with 15pf load  
. Operating frequency up to 100MHz with 50pf load  
technology to achieve higher than 1.125GHz TTL  
/CMOS output frequency with less than 1.8ns  
propagation delay.  
This dual Octal transparent D-type latches are designed  
for 1.65-V to 3.6-V VCC operation.  
. VCC Operates from 1.65V to 3.6V  
. Propagation delay < 1.8ns max with 15pf load  
. Low input capacitance: 4pf typical  
Inputs can be driven from either 3.3V or 5V devices.  
This feature allows the use of these devices as  
translators in a mixed 3.3V/5V system environment.  
. Available in 20pin TSSOP package  
. Available in 20pin Ceramic Dual Flatpack  
. Available in 20pin Leadless Ceramic Chip Carrier  
Pin Configuration  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1Q  
VCC  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
LE  
3
2
1 20 19  
18  
1D  
2D  
2Q  
3Q  
3D  
4D  
8D  
7D  
7Q  
6Q  
6D  
4
5
6
7
8
2D  
17  
16  
15  
14  
2Q  
3Q  
3D  
9 10 11 12 13  
4D  
4Q  
GND  
Pin Description  
Logic Block Diagram  
INPUTS  
OUTPUT  
Q
1
OE  
OE  
LE  
D
11  
LE  
L
L
H
H
L
H
L
H
L
C1  
1D  
2
1Q  
3
1D  
L
X
X
Q0  
Z
H
X
To Seven Other Channels  
1
Copyright © Potato Semiconductor Corporation  

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