Datasheet > PO74G304A

PO74G304A

更新时间： 2024-11-15 06:04:35

品牌	Logo	应用领域
POTATO		驱动器时钟
页数	文件大小	规格书
6页	578K
描述
3.3V 1:4 CMOS Clock Buffered Driver

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PO74G304A 数据手册

PO74G304A

3.3V 1:4 CMOS Clock Buffered Driver

07/31/06

700MHz TTL/CMOS Potato Chip

FEATURES:

DESCRIPTION:

Potato Semiconductor’s PO74G304A is designed for

world top performance using submicron CMOS technol-

ogy to achieve 700MHz TTL output frequency with less

than 100ps output pin to pin skew.

• Patented technology

• Operating frequency up to 700MHz with 2pf load

• Operating frequency up to 650MHz with 5pf load

• Operating frequency up to 450MHz with 15pf load

• Operating frequency up to 100MHz with 50pf load

• Very low output pin to pin skew < 100ps Max

• Very low pulse skew < 150ps Max

• VCC = 1.65V to 3.6V

• Propagation delay < 2.0ns max with 15pf load

• Low input capacitance: 3pf typical

• 1:4 fanout

PO74G304A is a 3.3V CMOS 1 input to 4 outputs

Buffered driver to achieve 700MHz output frequency.

Typical applications are clock and signal distribution.

They are used for networking and communications

applications.

Inputs can be driven from either 3.3V or 5V devices.

This feature allows the use of these devices as translators

in a mixed 3.3V/5V system environment.

• Packaging (Pb-free & Green available)

• Available in 8-pin TSSOP package

Pin Configuration

Logic Block Diagram

CLK_IN

VDD

GND

CLK_IN

Pin Description

FUNCTION TABLE

Pin#

Description

INPUTS

OUTPUT

5V Tolerant clock input

CLKIN

1Y (0:3)

Active High Output Enable.

LVCMOS level outputs

Groun

3,5,7,8

3.3V powe

12 3 4 5 6

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