Datasheet > PO74G112ATU

PO74G112ATU

更新时间： 2024-11-15 06:04:35

品牌	Logo	应用领域
POTATO		触发器
页数	文件大小	规格书
6页	579K
描述
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET

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中文翻译

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技术参数
数据手册

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PO74G112ATU 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.75
Base Number Matches：	1

PO74G112ATU 数据手册

PO74G112A

DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP

WITH CLEAR AND PRESET

04/19/09

74 Series GHz Logic

FEATURES:

DESCRIPTION:

. Patented technology

. Specified From –40°C to 85°C, –40°C to 125°C,

and –55°C to 125°C

. Operating frequency up to 750MHz with 15pf load

. VCC Operates from 1.65V to 3.6V

. Propagation delay < 2ns max with 15pf load

. Low input capacitance: 4pf typical

. Latch-Up Performance Exceeds 250 mA Per

JESD 17

Potato Semiconductor’s PO74G112A is designed for

world top performance using submicron CMOS

technology to achieve 750MHz TTL /CMOS output

frequency with less than 2ns propagation delay.

This dual negative-edge-triggered J-K flip-flop is

designed for 1.65-V to 3.6-V V^CCoperation.

Inputs can be driven from either 3.3V or 5V devices.

This feature allows the use of these devices as

translators in a mixed 3.3V/5V system environment.

. ESD Protection Exceeds JESD 22

. 5000-VHuman-BodyModel (A114-A)

. 200-VMachineModel (A115-A)

. Available in 16pin 150mil wide SOIC package

. Available in 16pin 173mil wide TSSOP package

Logic Block Diagram

Pin Configuration

1CLK

1CLR

2CLR

2CLK

1PRE

1CLK

V_CC

1CLR

2CLR

2CLK

PRE

12 2K

2PRE

CLR

1PRE

GND

PRE

Pin Description

INPUTS

OUTPUTS

2PRE

PRE

CLR

CLK

CLR

GND

Q₀

↓

Q ₀

↓

Toggle

Q₀

Q ₀

12 3 4 5 6

中文翻译

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