Datasheet > PO74G126A

PO74G126A

更新时间： 2024-11-15 06:04:35

品牌	Logo	应用领域
POTATO		输出元件
页数	文件大小	规格书
6页	496K
描述
QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

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中文翻译

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数据手册

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PO74G126A 数据手册

PO74G126A

QUADRUPLE BUS BUFFER GATE

WITH 3-STATE OUTPUTS

02/07/07

74 Series GHz Logic

FEATURES:

DESCRIPTION:

. Patented technology

Potato Semiconductor’s PO74G126A is designed for

world top performance using submicron CMOS

technology to achieve 1.125GHz TTL /CMOS output

frequency with less than 1.5ns propagation delay.

This quadruple bus buffer gate is designed for 1.65-V

to 3.6-V VCC operation.

. Operating frequency up to 1.125GHz with 2pf load

. Operating frequency up to 700MHz with 5pf load

. Operating frequency up to 400MHz with 15pf load

. VCC Operates from 1.65V to 3.6V

. Propagation delay < 1.5ns max with 15pf load

. Low input capacitance: 4pf typical

The PO74G126A featuresindependent

linedriverswith3-stateoutputs. Eachoutput isdisabled-

whenthe associatedoutput-enable(OE)input islow.

. Available in 14pin 150mil wide SOIC package

Inputs can be driven from either 3.3V or 5V devices.

This feature allows the use of these devices as

translators in a mixed 3.3V/5V system environment.

Pin Configuration

Logic Block Diagram

1OE

4OE

2OE

3OE

GND

3OE

Pin Description

INPUTS

OUTPUT

4OE

12 3 4 5 6

中文翻译

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