Datasheet > PO74G139ATU

PO74G139ATU

更新时间： 2024-11-15 06:04:35

品牌	Logo	应用领域
POTATO		/
页数	文件大小	规格书
6页	524K
描述
DUAL2-LINETO4-LINEDECODER/DEMULTIPLEXER

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中文翻译

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技术参数
数据手册

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PO74G139ATU 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.77
Base Number Matches：	1

PO74G139ATU 数据手册

PO74G139A

DUAL2-LINETO4-LINEDECODER/DEMULTIPLEXER

02/07/07

74 Series GHz Logic

FEATURES:

DESCRIPTION:

. Patented technology

Potato Semiconductor’s PO74G139A is designed for

world top performance using submicron CMOS

technology to achieve 1.125GHz TTL /CMOS output

frequency with less than 1.7ns propagation delay.

This quadruple bus buffer gate is designed for 1.65-V

to 3.6-V VCC operation.

. Operating frequency up to 1.125GHz with 2pf load

. Operating frequency up to 800MHz with 5pf load

. Operating frequency up to 350MHz with 15pf load

. VCC Operates from 1.65V to 3.6V

. Propagation delay < 1.7ns max with 15pf load

. Low input capacitance: 4pf typical

The PO74G139A comprises two individual 2-line to

4-line decoders in a single package. Theactive-

lowenable (G) input can be used as a data line in

demultiplexing applications. This decoder/ demulti-

plexer features fully buffered

. Available in 16 pin SOIC package

inputs, each of which represents only one normalized-

load to itsdriving circuit.

Inputs can be driven from either 3.3V or 5V devices.

This feature allows the use of these devices as

translators in a mixed 3.3V/5V system environment.

Pin Configuration

Logic Block Diagram

1Y0

1Y1

1Y2

Select

Inputs

1Y3

1Y0

1Y1

1Y2

1Y3

GND

Data

Outputs

2Y0

2Y1

2Y2

2Y3

2Y0

2Y1

2Y2

Select

Inputs

2Y3

Pin Description

INPUTS

OUTPUTS

SELECT

12 3 4 5 6

中文翻译

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