Datasheet > PO74G164245ASR

PO74G164245ASR

更新时间： 2024-11-15 06:04:35

品牌	Logo	应用领域
POTATO		/
页数	文件大小	规格书
10页	951K
描述
1.65v-3.6v, 16-bit Dual Supply Level Shifting Bidirectional Transceiver with 3 state outputs

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PO74G164245ASR 数据手册

PO74G164245A

1.65v-3.6v, 16-bit Dual Supply Level Shifting

Bidirectional Transceiver with 3 state outputs

02/01/09

74 Series GHz Logic

FEATURES:

DESCRIPTION:

Potato Semiconductor’s PO74G164245A is designed

for world top performance using submicron CMOS

technology to achieve 1GHz TTL /CMOS output

frequency.This Octal bus buffer gate is designed for

1.65v-3.6v, 16-bit Dual Supply Level ShiftingBidirec-

tional Transceiver with 3 state outputs operation.

. Patented technology

. Operating frequency up to 1GHz with 2pf load

. VCC Operates from 1.65V to 3.6V

. Low input capacitance: 5pf typical

. Available in 48pin TSSOP package

Contains two separate supply rails: B port (VCCB)

must set higher voltage (equal) then A port

(VCCA).This arrangement permits translation from a

1.8-2.5V to 3.3V environment.

. Comparator A inputs for accuracy signals

The PO74G164245A features independent 16-bit

Bidirectional Transceiver with 3 state outputs. Each

output is disabled when the associated output-

enable(OE) input is high.

Pin Configuration

Logic Block Diagram

V_CCA1

V_CCA2

1OE

1A0

1DIR

1B0

1DIR

2DIR

44k

(Typ.)

44k

1A1

1B1

1OE

2OE

(Typ.)

GND

1A2

GND

1B2

1A0

1A1

1A2

1A3

1A4

1A5

1A6

1A7

2A0

1A3

1B3

1B0

1B1

1B2

1B3

1B4

1B5

1B6

1B7

2B0

2B1

2B2

2B3

2B4

2B5

2B6

2B7

VCCA1

1A4

VCCB1

1B4

2A1

2A2

2A3

2A4

2A5

1A5

1B5

GND

1A6

GND

1B6

1B7

1A7

2B0

2A0

2B1

2A1

GND

2B2

GND

2B2

2B3

2A3

VCCB2

2B4

VCCA2

2A4

2B5

2A5

2A6

2A7

GND

2B6

GND

2A6

44k

(Typ.)

44k

(Typ.)

2B7

2A7

2DIR

2OE

Pin Description

Truth Table

Inputs

Outputs

Pin Name

Description

xOE

xDIR

3-State Output Enable Inputs (Active LOW

)

Bus B Data to Bus A

Bus A Data to Bus B

xDIR

Direction Control Input

Side A Inputs or 3-State Inputs

Side B Outputs or 3-State Outputs

Ground

XAX

xDIR

VCCAx

Comparator InputAx

disable

XBX

GND

V_CC

disable

Power

>0V

Enable

12 3 4 5 6 7...10

中文翻译

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