Datasheet > PO74G125ASU

PO74G125ASU

更新时间： 2024-11-15 06:04:35

品牌	Logo	应用领域
POTATO		输出元件
页数	文件大小	规格书
6页	499K
描述
QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

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中文翻译

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技术参数
数据手册

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PO74G125ASU 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.79
Base Number Matches：	1

PO74G125ASU 数据手册

PO74G125A

QUADRUPLE BUS BUFFER GATES

WITH 3-STATE OUTPUTS

07/26/06

74 Series GHz Logic

FEATURES:

DESCRIPTION:

. Patented technology

Potato Semiconductor’s PO74G125A is designed for

world top performance using submicron CMOS

technology to achieve 1.125GHz TTL /CMOS output

frequency with less than 1.5ns propagation delay.

This quadruple bus buffer gate is designed for 1.65-V

to 3.6-V VCC operation.

The PO74G125A features independent line drivers with

3-state outputs. Each output is disabled when the

associated output-enable (OE) input is high. To ensure

the high-impedance state during power up or power

down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is

determined by the current-sinking capability of

the driver.

. Operating frequency up to 1.125GHz with 2pf load

. Operating frequency up to 550MHz with 5pf load

. Operating frequency up to 300MHz with 15pf load

. VCC Operates from 1.65V to 3.6V

. Propagation delay < 1.5ns max with 15pf load

. Low input capacitance: 4pf typical

. Available in 14pin 150mil wide SOIC package

Inputs can be driven from either 3.3V or 5V devices.

This feature allows the use of these devices as

translators in a mixed 3.3V/5V system environment.

Pin Configuration

Logic Block Diagram

1OE

4OE

2OE

3OE

GND

3OE

Pin Description

INPUTS

OUTPUT

4OE

12 3 4 5 6

中文翻译

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PO74G126ASU	POTATO	获取价格	QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
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