Datasheet > PO74G02ASR

PO74G02ASR

更新时间： 2024-11-15 06:04:35

品牌	Logo	应用领域
POTATO		输入元件
页数	文件大小	规格书
6页	551K
描述
QUADRUPLE 2-INPUT POSITIVE-NOR GATES

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中文翻译

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技术参数
数据手册

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PO74G02ASR 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.78
Base Number Matches：	1

PO74G02ASR 数据手册

PO54G02A, PO74G02A

QUADRUPLE 2-INPUT POSITIVE-NOR GATES

10/05/07

54, 74 Series GHz Logic

FEATURES:

DESCRIPTION:

Potato Semiconductor’s PO74G02A is designed for

world top performance using submicron CMOS

technology to achieve 900MHz TTL /CMOS output

frequency with less than 1.5ns propagation delay.

. Patented technology

. Specified From –40°C to 85°C, –40°C to 125°C,

and –55°C to 125°C

. Operating frequency up to 900MHz with 2pf load

. Operating frequency up to 700MHz with 5pf load

. Operating frequency up to 400MHz with 15pf load

. VCC Operates from 1.65V to 3.6V

This quadruple 2-input positive-NOR gate is designed

for 1.65-V to 3.6-V VCC operation.

. Propagation delay < 1.5ns max with 15pf load

The PO74G02A performs the Boolean function

Y= A + B or Y= A · B in positive logic.

. Low input capacitance: 4pf typical

. Latch-Up Performance Exceeds 250 mA Per

JESD 17

. ESD Protection Exceeds JESD 22

. 5000-VHuman-BodyModel (A114-A)

. 200-VMachineModel (A115-A)

Inputs can be driven from either 3.3V or 5V devices.

This feature allows the use of these devices as

translators in a mixed 3.3V/5V system environment.

. Available in 14pin 150mil wide SOIC package

. Available in 14pin Ceramic Dual Flatpack

. Available in 20pin Leadless Ceramic Chip Carrier

Pin Configuration

1 20 19

15 NC

9 10 11 12 13

GND

Pin Description

Logic Block Diagram

INPUTS

OUTPUT

12 3 4 5 6

中文翻译

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