Datasheet > PO74G08ASIU

PO74G08ASIU

更新时间： 2024-11-15 06:04:35

品牌	Logo	应用领域
POTATO		输入元件
页数	文件大小	规格书
6页	537K
描述
QUADRUPLE 2-INPUT POSITIVE-AND GATES

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数据手册

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PO74G08ASIU 数据手册

PO54G08A, PO74G08A

QUADRUPLE 2-INPUT POSITIVE-AND GATES

09/12/07

54, 74 Series GHz Logic

FEATURES:

DESCRIPTION:

. Patented technology

. Specified From –40°C to 85°C, –40°C to 125°C,

and –55°C to 125°C

Potato Semiconductor’s PO74G08A is designed for

world top performance using submicron CMOS

technology to achieve 1.125GHz TTL /CMOS output

frequency with less than 1.5ns propagation delay.

This quadruple 2-input positive-AND gate is designed

. Operating frequency up to 1.125GHz with 2pf load

. Operating frequency up to 750MHz with 5pf load

. Operating frequency up to 350MHz with 15pf load for 1.65-V to 3.6-V VCC operation.

The PO74G08A performs the Boolean function

Y= A · B or Y= A + B in positive logic.

. VCC Operates from 1.65V to 3.6V

. Propagation delay < 1.5ns max with 15pf load

. Low input capacitance: 4pf typical

. Latch-Up Performance Exceeds 250 mA Per

JESD 17

Inputs can be driven from either 3.3V or 5V devices.

This feature allows the use of these devices as transla-

tors in a mixed 3.3V/5V system environment.

. ESD Protection Exceeds JESD 22

. 5000-VHuman-BodyModel (A114-A)

. 200-VMachineModel (A115-A)

. Available in 14pin 150mil wide SOIC package

. Available in 14pin Ceramic Dual Flatpack

. Available in 20pin Leadless Ceramic Chip Carrier

Pin Configuration

2 1 20 19

11 4Y

9 10 11 12 13

GND

Pin Description

Logic Block Diagram

INPUTS

OUTPUT

12 3 4 5 6

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PO74G112ASU	POTATO	获取价格	DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET
PO74G112ATR	POTATO	获取价格	DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET
PO74G112ATU	POTATO	获取价格	DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET