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PO74G00ASI PDF预览

PO74G00ASI

更新时间: 2024-11-15 06:04:35
品牌 Logo 应用领域
其他 - ETC /
页数 文件大小 规格书
6页 507K
描述
54, 74 Series GHz Logic

PO74G00ASI 数据手册

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PO54G00A, PO74G00A  
QUADRUPLE 2-INPUT POSITIVE-NAND GATE  
09/12/07  
54, 74 Series GHz Logic  
FEATURES:  
DESCRIPTION:  
. Patented technology  
. Specified From –40°C to 85°C, –40°C to 125°C,  
and –55°C to 125°C  
Potato Semiconductor’s PO74G00A is designed for  
world top performance using submicron CMOS  
technology to achieve 1.125GHz TTL/CMOS output  
frequency with less than 1.5ns propagation delay.  
. Operating frequency up to 1.125GHz with 2pf load  
. Operating frequency up to 750MHz with 5pf load  
. Operating frequency up to 350MHz with 15pf load  
This quadruple 2-input positive-NAND gate is  
designed for 1.65-V to 3.6-V VCC operation.  
. VCC Operates from 1.65V to 3.6V  
. Propagation delay < 1.5ns max with 15pf load  
. Low input capacitance: 4pf typical  
. Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
. ESD Protection Exceeds JESD 22  
. 2000-VHuman-BodyModel (A114-A)  
. 200-VMachineModel (A115-A)  
The PO74G00A performs the Boolean function  
Y= A · B or Y= A + B in positive logic.  
Inputs can be driven from either 3.3V or 5V devices.  
This feature allows the use of these devices as  
translators in a mixed 3.3V/5V system environment.  
. 1000-VCharged-DeviceModel (C101)  
. Available in 14pin 150mil wide SOIC package  
. Available in 14pin Ceramic Dual Flatpack  
. Available in 20pin Leadless Ceramic Chip Carrier  
Pin Configuration  
1A  
1B  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
V
CC  
3
2 1 20 19  
18  
4B  
4A  
4Y  
3B  
3A  
3Y  
4A  
NC  
4Y  
NC  
3B  
1Y  
NC  
2A  
4
5
6
7
8
1Y  
17  
16  
15  
14  
2A  
NC  
2B  
2B  
2Y  
9 10 11 12 13  
GND  
8
Pin Description  
Logic Block Diagram  
INPUTS  
OUTPUT  
Y
A
H
L
B
H
X
L
A
B
L
H
H
Y
X
1
Copyright © 2005-2007, Potato Semiconductor Corporation  

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