Datasheet > PLL1700E

PLL1700E

更新时间： 2024-11-09 02:58:39

品牌	Logo	应用领域
德州仪器 - TI		时钟光电二极管外围集成电路晶体
页数	文件大小	规格书
15页	383K
描述
MULTI-CLOCK GENERATOR

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中文翻译

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数据手册

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PLL1700E 数据手册

PLL1700

49%

FPO

SBOS096A – JANUARY 1998 – REVISED MAY 2007

MULTI-CLOCK GENERATOR

FEATURES

● 27MHz MASTER CLOCK INPUT

DESCRIPTION

The PLL1700 is a low cost, multi-clock generator Phase

Lock Loop (PLL).

● GENERATED AUDIO SYSTEM CLOCK:

SCKO1: 33.8688MHz (Fixed)

SCKO2: 256f_S

The PLL1700 can generate four systems clocks from a

27MHz reference input frequency.

SCKO3: 384f_S

SCKO4: 768f_S

The device gives customers both cost and space savings

by eliminating external components and enables custom-

ers to achieve the very low jitter performance needed for

high-performance audio digital-to-analog converters

(DACs) and/or analog-to-digital converters (ADCs).

● ZERO PPM ERROR OUTPUT CLOCKS

● LOW CLOCK JITTER: 150ps at SCKO3

● MULTIPLE SAMPLING FREQUENCIES:

f_S= 32kHz, 44.1kHz, 48kHz, 64kHz,

88.2kHz, 96kHz

The PLL1700 is ideal for MPEG-2 applications that use a

27MHz master clock such as DVD players, DVD add-on

cards for multimedia PCs, digital HDTV systems, and set-

top boxes.

● +3.3V CMOS LOGIC INTERFACE

● DUAL POWER SUPPLIES: +5V and +3.3V

● SMALL PACKAGE: 20-Lead SSOP

MODE

V_DDPGNDP V_DDBGNDB V_DDGND

Power Supply

Mode

Control

I/F

Reset

OSC

RST

PLL2

XT1

XT2

PLL1

Counter P

SCKO3

Counter Q

SCKO2

MCKO MCKO

SCKO4

SCKO1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

www.ti.com

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