PLL130-68/-69
High Speed Translator Buffers: Single ended to PECL or LVDS
FEATURES
PIN CONFIGURATION
(TOP VIEW)
•
•
Differential PECL (PLL130-68) or LVDS
(PLL130-69) output.
Accepts any single-ended REFIN input (with
as low as 100mV swing).
Internal AC coupling of REFIN
Input range from 1.0MHz to 1.0 GHz.
No Vref required.
No external current source required.
2.5 to 3.3V operation.
Available in 3x3mm QFN.
16
15
14
13
•
•
•
•
•
•
NC
1
2
3
12
11
10
9
NC
Q
REFIN
NC
PLL130-6x
Q_bar
OESEL
4
NC
5
6
7
8
OUTPUT ENABLE LOGICAL LEVELS
PLL130-68
DESCRIPTION
The PLL130-68 and PLL130-69 are low cost,
high performance, high speed, translator buffers
that reproduce any input frequency from DC to
1.0GHz. They provide a pair of differential out-
puts (PECL for PLL130-68 or LVDS for PLL130-
69). Thanks to an internal AC coupling of the
reference input (REFIN), any input signal with at
least 100mV swing can be used as reference
signal, regardless of its DC value. These chips
are ideal for conversion from clipped sine wave,
TTL, CMOS, or differential signal to LVDS or
PECL.
OESEL
OECTRL
OUTPUT STATE
Output enabled
Tri-state
0 (Default)
0 (Default)
1
0
Tri-state
1
1 (Default)
Output enabled
OECTRL input: Logical states defined by PECL levels.
PLL130-69
OESEL
OECTRL
OUTPUT STATE
Tri-state
0
0 (Default)
1 (Default)
0 (Default)
1
Output enabled
Output enabled
Tri-state
1
OECTRL input: Logical states defined by CMOS levels.
BLOCK DIAGRAM
Q_BAR
Q
AC
Input
Amplifier
REFIN
Coupling
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 1