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PLL130-05SI

更新时间： 2024-11-10 10:08:39

品牌	Logo	应用领域
PLL		转换器
页数	文件大小	规格书
4页	208K
描述
High Speed Translator Buffer to PECL (Enable Low)

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数据手册

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PLL130-05SI 数据手册

PLL130-05

High Speed Translator Buffer to PECL (Enable Low)

FEATURES

PIN CONFIGURATION

(TOP VIEW)

•

Differential PECL output

Single AC coupled input (min. 100mV swing).

Input range from DC to 1.0 GHz.

2.5V to 3.3V operation.

Available in 3x3mm QFN.

GND

PECL_BAR

VDD

¹⁴PLL130-05

GND

PECL

OE^V

GND

DESCRIPTION

The PLL130-05 is a low cost, high performance,

high speed, buffer that reproduces any input fre-

quency from DC to 1.3GHz. It provides one pair

of differential PECL outputs. Any input signal

with at least 100mV swing can be used as refer-

ence signal. This chip is ideal for conversion

from sine wave, TTL, CMOS, or LVDS to PECL.

Note: denotes internal pull down

BLOCK DIAGRAM

PECL_BAR

PECL

Input

Amplifier

REF_IN

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 1

12 3 4

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