PLL130-08QC-R

更新时间： 2024-09-21 10:08:39

品牌	Logo	应用领域
PLL		时钟驱动器转换器接口集成电路
页数	文件大小	规格书
5页	239K
描述
High Speed Translator Buffer to PECL

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技术参数
数据手册

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PLL130-08QC-R 技术参数

生命周期：	Transferred	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.8
Is Samacsys：	N	Base Number Matches：	1

PLL130-08QC-R 数据手册

PLL130-08

High Speed Translator Buffer to PECL

FEATURES

PIN CONFIGURATION

(TOP VIEW)

•

Differential PECL output

Single AC coupled input (min. 100mV swing).

Input range from DC to 1.0 GHz.

2.5V to 3.3V operation.

GND

REF_IN

GND

VDD

Available in 8-Pin SOIC or 3x3mm QFN.

GND

PECL_BAR

VDD

PECL

DESCRIPTION

The PLL130-08 is a low cost, high performance,

high speed, buffer that reproduces any input fre-

quency from DC to 1.0GHz. It provides a pair of

differential PECL output. Any input signal with at

least 100mV swing can be used as reference

signal. This chip is ideal for conversion from sine

wave, TTL, CMOS, or LVDS to PECL.

GND

PECL_BAR

VDD

¹⁴PLL130-08

GND

PECL

GND

OE^

Note: ^ denotes internal pull up

BLOCK DIAGRAM

PECL_BAR

PECL

Input

REF_IN

Amplifier

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 1

12 3 4 5

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与PLL130-08QC-R相关器件

型号	品牌	获取价格	描述	数据表
PLL130-08QI	PLL	获取价格	High Speed Translator Buffer to PECL
PLL130-08SC	PLL	获取价格	High Speed Translator Buffer to PECL
PLL130-08SC-R	PLL	获取价格	High Speed Translator Buffer to PECL
PLL130-08SI	PLL	获取价格	High Speed Translator Buffer to PECL
PLL130-09	PLL	获取价格	High Speed Translator Buffer to LVDS
PLL130-09QC	PLL	获取价格	High Speed Translator Buffer to LVDS
PLL130-09QC-R	PLL	获取价格	High Speed Translator Buffer to LVDS
PLL130-09QI	PLL	获取价格	High Speed Translator Buffer to LVDS
PLL130-09SC	PLL	获取价格	High Speed Translator Buffer to LVDS
PLL130-09SC-R	PLL	获取价格	High Speed Translator Buffer to LVDS