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PLL130-07ASC-R PDF预览

PLL130-07ASC-R

更新时间: 2024-11-10 19:02:23
品牌 Logo 应用领域
PLL 光电二极管
页数 文件大小 规格书
5页 256K
描述
Interface Circuit, PDSO8,

PLL130-07ASC-R 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:SOP, SOP8,.25Reach Compliance Code:unknown
风险等级:5.68JESD-30 代码:R-PDSO-G8
端子数量:8最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
电源:3 V认证状态:Not Qualified
子类别:Other Interface ICs标称供电电压:3 V
表面贴装:YES温度等级:COMMERCIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUALBase Number Matches:1

PLL130-07ASC-R 数据手册

 浏览型号PLL130-07ASC-R的Datasheet PDF文件第2页浏览型号PLL130-07ASC-R的Datasheet PDF文件第3页浏览型号PLL130-07ASC-R的Datasheet PDF文件第4页浏览型号PLL130-07ASC-R的Datasheet PDF文件第5页 
High Speed Translator Buffer to LVCMOS  
FEATURES  
PIN CONFIGURATION  
(TOP VIEW)  
LVCMOS output  
Selectable Drive capability  
Drive 15pF or 30pF output load  
Single AC coupled input (min. 100mV swing).  
Accepts LVCMOS or Sine Wave inputs.  
Input range from 0 to 200 MHz.  
OE High (PLL130-07) or OE Low (PL130-07A)  
Enable  
GND  
REF_IN  
GND  
DRV_SEL^  
VDD  
1
2
3
4
8
7
6
5
GND  
VDD  
CLK_OUT  
SOP-8L  
2.5V to 3.3V operation.  
Available in 8-Pin SOP, 8-Pin TSSOP and  
VDD  
DRV_SEL  
GND  
CLK_OUT  
VDD  
1
8
3x3mm 16-Pin QFN.  
2
3
4
7
6
5
DNC  
DESCRIPTION  
OE  
FIN  
The PLL130-07 is a low cost, high performance, high  
speed, buffer that reproduces any input frequency  
from 0 to 200MHz. It provides an LVCMOS output  
with 15pF output load drive capability. Any input sig-  
nal with at least 100mV swing can be used as refer-  
ence signal. This chip is ideal for conversion from  
sine wave to LVCMOS.  
TSSOP-8L  
12  
11  
10  
9
13  
8
DRV_SEL  
CLK_OUT  
14  
15  
7
VDD  
N/C  
GND  
GND  
PLL130-07(A)  
6
16  
5
GND  
OE  
1
2
3
4
BLOCK DIAGRAM  
Input  
REF_IN  
CLK_OUT  
Amplifier  
OE  
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/14/07 Page 1  

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