Datasheet > PLL130-69

PLL130-69

更新时间： 2024-11-08 10:08:39

品牌	Logo	应用领域
PLL		/
页数	文件大小	规格书
5页	224K
描述
High Speed Translator Buffers: Single ended to PECL or LVDS

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数据手册

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PLL130-69 数据手册

PLL130-68/-69

High Speed Translator Buffers: Single ended to PECL or LVDS

FEATURES

PIN CONFIGURATION

(TOP VIEW)

•

Differential PECL (PLL130-68) or LVDS

(PLL130-69) output.

Accepts any single-ended REFIN input (with

as low as 100mV swing).

Internal AC coupling of REFIN

Input range from 1.0MHz to 1.0 GHz.

No Vref required.

No external current source required.

2.5 to 3.3V operation.

Available in 3x3mm QFN.

•

REFIN

PLL130-6x

Q_bar

OESEL

OUTPUT ENABLE LOGICAL LEVELS

PLL130-68

DESCRIPTION

The PLL130-68 and PLL130-69 are low cost,

high performance, high speed, translator buffers

that reproduce any input frequency from DC to

1.0GHz. They provide a pair of differential out-

puts (PECL for PLL130-68 or LVDS for PLL130-

69). Thanks to an internal AC coupling of the

reference input (REFIN), any input signal with at

least 100mV swing can be used as reference

signal, regardless of its DC value. These chips

are ideal for conversion from clipped sine wave,

TTL, CMOS, or differential signal to LVDS or

PECL.

OESEL

OECTRL

OUTPUT STATE

Output enabled

Tri-state

0 (Default)

Tri-state

1 (Default)

Output enabled

OECTRL input: Logical states defined by PECL levels.

PLL130-69

OESEL

OECTRL

OUTPUT STATE

Tri-state

0 (Default)

1 (Default)

0 (Default)

Output enabled

Tri-state

OECTRL input: Logical states defined by CMOS levels.

BLOCK DIAGRAM

Q_BAR

Input

Amplifier

REFIN

Coupling

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 1

12 3 4 5

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