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PLL130-07

更新时间： 2024-11-28 10:08:39

品牌	Logo	应用领域
PLL		驱动器
页数	文件大小	规格书
5页	231K
描述
High Speed Translator Buffer to CMOS (Selectable Drive)

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数据手册

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PLL130-07 数据手册

PLL130-07

High Speed Translator Buffer to CMOS (Selectable Drive)

FEATURES

PIN CONFIGURATION

(TOP VIEW)

•

CMOS output

Selectable Drive capability (15pF or 30pF

output load).

GND

REF_IN

GND

DRIV_SEL^

VDD

•

Single AC coupled input (min. 100mV swing).

Input range from DC to 200 MHz.

2.5V to 3.3V operation.

GND

Available in 8-Pin SOIC and 3x3mm QFN.

VDD

CLK_OUT

DESCRIPTION

The PLL130-07 is a low cost, high performance,

high speed, buffer that reproduces any input fre-

quency from DC to 200MHz. It provides CMOS

output with 15pF output load drive capability.

Any input signal with at least 100mV swing can

be used as reference signal. This chip is ideal

for conversion from sine wave to CMOS.

DRIV_SEL^

CLK_OUT

VDD

¹⁴PLL130-07

GND

N/C

GND

OE^

Note: ^ denotes internal pull up

BLOCK DIAGRAM

Input

Amplifier

REF_IN

CLK_OUT

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 1

12 3 4 5

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PLL130-07QC	PLL	获取价格	High Speed Translator Buffer to CMOS (Selectable Drive)
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PLL130-07SC-R	PLL	获取价格	High Speed Translator Buffer to CMOS (Selectable Drive)