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PI74AVCH16260KX PDF预览

PI74AVCH16260KX

更新时间： 2024-11-21 20:02:39
品牌 Logo 应用领域
百利通 - PERICOM 光电二极管逻辑集成电路电视
页数 文件大小 规格书
5页 329K
描述
Multiplexer And Demux/Decoder, AVC Series, 12-Func, CMOS, PDSO48, 0.173 INCH, PLASTIC, TVSOP-48

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PI74AVCH16260KX 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：TSSOP,针数：48
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.84
系列：AVCJESD-30 代码：R-PDSO-G48
JESD-609代码：e0长度：9.7 mm
逻辑集成电路类型：MULTIPLEXER AND DEMUX/DECODER功能数量：12
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.4 mm端子位置：DUAL
宽度：4.4 mmBase Number Matches：1

PI74AVCH16260KX 数据手册

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ADVANCE INFORMATION  
PI74AVC16260  
PI74AVCH16260  
12-Bit To 24-Bit Multiplexed D-Type Latch  
with 3-State Outputs  
Product Features  
ProductDescription  
PericomSemiconductor’sPI74AVCseriesoflogiccircuitsare  
producedusingtheCompany’sadvanced0.35micronCMOS  
technology, achieving industry leading speed.  
• Designed for low voltage operation,  
V
CC  
from 1.65V to 3.6V  
• Sub 2.0ns delays at 2.5V and 3.3V  
The 12-bit to 24-bit multiplexed D-type latch is used in  
applicationswheretwoseparatedatapathsmustbemultiplexed  
onto, or demultiplexed from, a single data path.  
• Dynamic Impedance Control on outputs,  
current drive > ±24mA at 2.5V V  
CC  
• Patented noise reduction circuit  
• I/O Tolerant to 3.6V, Inputs and Outputs  
for mixed voltage systems  
Typical applications include multiplexing and/or demulti-  
plexing address and data information in microprocessor or  
bus-interface applications. This device is also useful in  
memory-interleavingapplications.  
• Supports live insertion  
• Industrial operation at –40°C to +85°C  
• Available Packages:  
Three12-bitI/Oports(A1-A12,1B1-1B12,and2B1-2B12)are  
available for address and/or data transfer. The output-enable  
(OE1B, OE2B, and OEA) inputs control the bus transceiver  
functions. The OE1B and OE2B control signals also allow  
bank control in the A-to-B direction.  
– 48-pin 240 mil wide plastic TSSOP (A48)  
– 48-pin 173 mil wide plastic TVSOP (K48)  
Address and/or data information can be stored using the  
internal storage latches. The latch-enable (LE1B, LE2B,  
LEA1B, and LEA2B) inputs are used to control data storage.  
Whenthelatch-enableinputisHIGH,thelatchistransparent.  
When the latch-enable input goes LOW, the data present at  
the inputs is latched and remains latched until the latch-  
enable input is returned HIGH.  
Logic Block Diagram  
2
LE1B  
27  
LE2B  
30  
LEA1B  
55  
To ensure the high-impedance state during power up or  
LEA2B  
power down, OE should be tied to V through a pullup  
56  
CC  
OE2B  
resistor,theminimumvalueoftheresistorisdeterminedbythe  
current-sinking capability of the driver.  
29  
OE1B  
Active bus-hold circuitry is provided to hold unused or  
floating data inputs at a valid logic level.  
1
OEA  
28  
SEL  
The PI74AVCH16260 has “Bus Hold” which retains the data  
input’s last state whenever the data input goes to high-  
impedance preventing “floating” inputs and eliminating the  
need for pullup/down resistors.  
G1  
C1  
1D  
23  
8
1
1
1
B
1
1
A1  
C1  
1D  
6
2B  
C1  
1D  
C1  
1D  
TO 11 OTHER CHANNELS  
PSXXXX 02/02/99  
1
12345

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 		Registered Bus Transceiver, AVC Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 0.173 IN
PI74AVCH16721KX PERICOM

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 		Bus Driver, AVC Series, 1-Func, 20-Bit, True Output, CMOS, PDSO48, 0.173 INCH, PLASTIC, TV
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