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PI74ALVTC16244V PDF预览

PI74ALVTC16244V

更新时间: 2024-10-27 23:27:39
品牌 Logo 应用领域
百利通 - PERICOM 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 238K
描述
Quad 4-Bit Buffer/Driver

PI74ALVTC16244V 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:SSOP包装说明:0.300 INCH, 0.635 MM PITCH, PLASTIC, SSOP-48
针数:48Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.91Is Samacsys:N
控制类型:ENABLE LOW系列:ALVT
JESD-30 代码:R-PDSO-G48JESD-609代码:e0
长度:15.875 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.064 A
位数:4功能数量:4
端口数量:2端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP48,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 VProp。Delay @ Nom-Sup:2.4 ns
传播延迟(tpd):3.5 ns认证状态:Not Qualified
座面最大高度:2.794 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):1.8 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
Base Number Matches:1

PI74ALVTC16244V 数据手册

 浏览型号PI74ALVTC16244V的Datasheet PDF文件第2页浏览型号PI74ALVTC16244V的Datasheet PDF文件第3页浏览型号PI74ALVTC16244V的Datasheet PDF文件第4页浏览型号PI74ALVTC16244V的Datasheet PDF文件第5页浏览型号PI74ALVTC16244V的Datasheet PDF文件第6页浏览型号PI74ALVTC16244V的Datasheet PDF文件第7页 
PI74ALVTC16244  
1.8/2.5/3.3V 16-Bit Buffer/Driver  
with 3-State Outputs  
Product Features  
Product Description  
• PI74ALVTC family is designed for low voltage operation,  
VDD = 1.8Vto3.6V  
Pericom Semiconductor’s PI74ALVTC series of logic circuits  
are produced in the Company’s advanced 0.35 micron CMOS  
technology, achieving industry leading speed.  
• Supports Live Insertion  
The PI74ALVTC16244 buffer/driver is designed specifically to  
improve both the performance and density of 3-state memory  
address drivers, clock drivers, and bus-oriented receivers and  
transmitters.  
• 3.6V I/O Tolerant Inputs and Outputs  
• Bus Hold  
• HighDrive,-32/64mA@3.3V  
• Uses patented noise reduction circuitry  
• Power-off high impedance inputs and outputs  
• Industrial operation at –40°C to +85°C  
• Packagesavailable:  
Thedevicecanbeusedasfour4-bitbuffers,two8-bitbuffers,orone  
16-bit buffer. It provides true outputs and symmetrical active-low  
output-enable (OE) inputs.  
To ensure the high-impedance state during power up or power  
down, OE should be tied to Vdd through a pullup resistor; the  
minimum value of the resistor is determined by the current-sinking  
capability of the driver.  
–48-pin240milwideplasticTSSOP(A)  
–48-pin173milwideplastic TVSOP(K)  
–48-pin300milwideplastic SSOP(V)  
The family offers both I/O Tolerant, which allows it to operate in  
mixed 1.8/3.6V systems, and “Bus Hold,” which retains the data  
input’s last state whenever the data input goes to high-impedance,  
preventing “floating” inputs and eliminating the need for pullup/  
down resistors.  
Logic Block Diagram  
1
25  
1OE  
3OE  
47  
46  
2
3
36  
35  
13  
14  
1A  
1A  
1A  
1A  
1
2
3
4
1
1
1
1
Y
Y
Y
Y
1
2
3
4
3
3
3
3
A
A
A
A
1
2
3
4
3Y  
3Y  
3Y  
3
Y
1
2
3
4
44  
43  
5
6
33  
32  
16  
17  
24  
30  
48  
41  
2
OE  
4OE  
19  
20  
8
2A  
2A  
2A  
2A  
1
2
3
4
2Y  
2Y  
2Y  
2
Y
1
2
3
4
4
4
4
4
A
A
A
A
1
2
3
4
4Y  
4Y  
4Y  
4
Y
1
2
3
4
29  
27  
26  
40  
38  
37  
9
11  
12  
22  
23  
PS8159D  
11/23/98  
1

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