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PI74ALVTC16260AX PDF预览

PI74ALVTC16260AX

更新时间： 2024-10-28 19:46:03
品牌 Logo 应用领域
百利通 - PERICOM 光电二极管逻辑集成电路
页数 文件大小 规格书
8页 396K
描述
Multiplexer And Demux/Decoder, ALVC/VCX/A Series, 12-Func, CMOS, PDSO56, 0.240 INCH, PLASTIC, TSSOP-56

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中文翻译

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PI74ALVTC16260AX 技术参数

生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP,针数：56
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.84
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G56
JESD-609代码：e0长度：14 mm
逻辑集成电路类型：MULTIPLEXER AND DEMUX/DECODER功能数量：12
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
宽度：6.1 mmBase Number Matches：1

PI74ALVTC16260AX 数据手册

 浏览型号PI74ALVTC16260AX的Datasheet PDF文件第2页浏览型号PI74ALVTC16260AX的Datasheet PDF文件第3页浏览型号PI74ALVTC16260AX的Datasheet PDF文件第4页浏览型号PI74ALVTC16260AX的Datasheet PDF文件第5页浏览型号PI74ALVTC16260AX的Datasheet PDF文件第6页浏览型号PI74ALVTC16260AX的Datasheet PDF文件第7页 
ADVANCE INFORMATION  
PI74ALVTC16260  
2.5V 12-Bit to 24-Bit Multiplexed  
D-Type Latch with 3-State Outputs  
ProductDescription  
Product Features  
Pericom Semiconductor’s PI74ALVTC series of logic circuits are  
produced using the Company’s advanced 0.35 micron CMOS  
technology, achieving industry leading speed.  
• PI74ALVTC16260isdesignedforlowvoltageoperation,  
V
DD  
=1.65Vto3.6V  
• Supports Live Insertion  
ThePI74ALVTC16260isa12-bitto24-bitmultiplexedD-typelatch  
• 3.6V I/O Tolerant Inputs and Outputs  
• Bus Hold  
designed for 1.65V to 3.6 V operation. It is used in applications  
DD  
where two separate datapaths must be multiplexed onto, or  
demultiplexed from, a single data path.  
• HighDrive,–32/64mA@3.3V  
• Uses patented noise reduction circuitry  
• Power-off high impedance inputs and outputs  
• Industrial operation at –40°C to +85°C  
• Packagesavailable:  
Typical applications include multiplexing and/or demulti-plexing  
address and data information in microprocessor or bus-interface  
applications. This device is also useful in memory-interleaving  
applications.  
Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are  
available for address and/or data transfer. The output-enable  
(OE1B,OE2B,andOEA)inputscontrolthebustransceiverfunctions.  
The OE1Band OE2Bcontrol signals also allowbank control in the  
A-to-Bdirection.  
–56-pin240-milwideplasticTSSOP(A56)  
–56-pin173-milwideplasticTVSOP(K56)  
Address and/or data information can be stored using the internal  
storagelatches.Thelatch-enable(LE1B,LE2B,LEA1B,andLEA2B)  
inputsareusedtocontroldatastorage. Whenthelatch-enableinput  
is HIGH, the latch is transparent. When the latch-enable input goes  
LOW, the data present at the inputs is latched and remains latched  
until the latch-enable input is returned HIGH.  
LogicBlockDiagram  
2
LE1B  
27  
LE2B  
30  
LEA1B  
55  
LEA2B  
56  
To ensure the high-impedance state during power up or power  
OE2B  
down, OE should be tied to V  
minimumvalue of the resistor is determined by the current-sinking  
capability of the driver.  
through a pullup resistor, the  
DD  
29  
OE1B  
1
OEA  
28  
The family offers both I/O Tolerant, which allows it to operate in  
mixed 1.65/3.6V systems, and “Bus Hold,” which retains the data  
input’s last state preventing “floating” inputs and eliminating the  
need for pullup/down resistors.  
SEL  
G1  
C1  
1D  
23  
8
1
1
1
B
B
1
1
A1  
C1  
1D  
6
2
C1  
1D  
C1  
1D  
TO 11 OTHER CHANNELS  
PXXXX  
04/11/00  
1
12345678

中文翻译

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