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PI6C2409-LI PDF预览

PI6C2409-LI

更新时间: 2024-11-28 22:26:03
品牌 Logo 应用领域
百利通 - PERICOM 时钟
页数 文件大小 规格书
8页 168K
描述
Zero-Delay Clock Buffer

PI6C2409-LI 数据手册

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PI6C2409  
Zero-Delay Clock Buffer  
ProductFeatures  
FunctionalDescription  
Maximumratedfrequency:133MHz  
Lowcycle-to-cyclejitter  
The PI6C2409 is a PLL based, zero-delay buffer, with the ability  
to distribute nine outputs of up to 133MHz at 3.3V.  
AlltheoutputsaredistributedfromasingleclockinputCLKINand  
outputOUT0performszerodelaybyconnectingafeedbacktoPLL.  
Input to output delay, less than 200ps  
Internal feedback allows outputs to be synchronized  
PI6C2409 has two banks of four outputs that can be controlled by  
theselectioninputs,SEL1&SEL2.Italsohasapowersparingfeature:  
when input SEL1 is 0 and SEL2 is 1, PLL is turned off and all  
outputs are referenced from CLKIN. PI6C2409 is available in  
high drive and industrial environment versions.  
to the clock input  
Operatesat3.3VVDD  
Space-saving Packages:  
150-milSOIC (W)  
173-milTSSOP (L)  
An internal feedback on OUT0 is used to synchronize the  
outputs to the input; the relationship between loading of this signal  
and the outputs determines the input-output delay.  
PI6C2409 are characterized for both commercial and  
industrial operation  
BlockDiagram  
PinConfiguration  
OUT0  
CLKIN  
OUTA1  
OUTA2  
16  
1
2
3
4
5
6
7
8
OUT0  
PLL  
OUTA1  
OUTA2  
OUTA3  
OUTA4  
MUX  
CLKIN  
15 OUTA4  
14  
OUTA3  
16-Pin  
W,L  
13  
12  
11  
10  
9
V
V
GND  
DD  
DD  
GND  
OUTB1  
OUTB2  
SEL2  
SEL1  
SEL2  
Decode  
Logic  
OUTB4  
OUTB3  
SEL1  
OUTB1  
OUTB2  
OUTB3  
OUTB4  
PI6C2409(-1, -1H)  
PS8613A  
07/15/03  
1

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