5秒后页面跳转
捷配首页

Datasheet > PEX8624-AB50BCF
PEX8624-AB50BCF PDF预览

PEX8624-AB50BCF

更新时间： 2024-11-13 15:47:47
品牌 Logo 应用领域
PLX PC外围集成电路
页数 文件大小 规格书
4页 216K
描述
PCI Bus Controller, CMOS, PBGA324, 19 X 19 MM, LEAD FREE, FCBGA-324

阅读下载

中文翻译

获取价格

PEX8624-AB50BCF 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：BGA,针数：324
Reach Compliance Code：unknown风险等级：5.64
总线兼容性：I2CJESD-30 代码：S-PBGA-B324
端子数量：324封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装形状：SQUARE
封装形式：GRID ARRAY峰值回流温度（摄氏度）：NOT SPECIFIED
表面贴装：YES技术：CMOS
端子形式：BALL端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIEDuPs/uCs/外围集成电路类型：BUS CONTROLLER, PCI
Base Number Matches：1

PEX8624-AB50BCF 数据手册

 浏览型号PEX8624-AB50BCF的Datasheet PDF文件第2页浏览型号PEX8624-AB50BCF的Datasheet PDF文件第3页浏览型号PEX8624-AB50BCF的Datasheet PDF文件第4页 
Version 1.0 2009  
PEX 8624  
PCIe Gen2, 5.0GT/s 24-lane, 6-port Switch  
Features  
ƒ PEX 8624 Vitals  
o 24-lane, 6-port PCIe Gen2 switch  
- Integrated 5.0 GT/s SerDes  
o 19 x 19mm2, 324-pin FCBGA package  
o Typical Power: 1.9 Watts  
The ExpressLaneTM PEX 8624 device offers PCI Express switching  
capability enabling users to add scalable high bandwidth, non-blocking  
interconnection to a wide variety of applications including  
workstations, storage systems, and communications platforms. The  
PEX 8624 is well suited for fan-out, aggregation, and peer-to-peer  
applications.  
ƒ PEX 8624 Key Features  
o Standards Compliant  
- PCI Express Base Specification, r2.0  
(backwards compatible w/ PCIe r1.0a/1.1)  
- PCI Power Management Spec, r1.2  
- Microsoft Vista Compliant  
- Supports Access Control Services  
- Dynamic link-width control  
- Dynamic SerDes speed control  
o High Performance  
- Non-blocking switch fabric  
- Full line rate on all ports  
- Packet Cut-Thru with 160ns max packet  
latency (x8 to x8)  
- 2KB Max Payload Size  
High Performance & Low Packet Latency  
The PEX 8624 architecture supports packet cut-thru with a maximum  
latency of 160ns (x8 to x8). This, combined with large packet memory and  
non-blocking internal switch architecture, provides full line rate on all ports  
for performance-hungry applications such as servers and switch fabrics.  
The low latency enables applications to achieve high throughput and  
performance. In addition to low latency, the device supports a max payload  
size of 2048 bytes, enabling the user to achieve even higher throughput.  
- Read Pacing (bandwidth throttling)  
- Dual-Cast  
o Flexible Configuration  
Data Integrity  
- Ports configurable as x1, x2, x4, x8  
- Registers configurable with strapping  
pins, EEPROM, I2C, or host software  
- Lane and polarity reversal  
- Compatible with PCIe 1.0a PM  
o Dual-Host & Fail-Over Support  
- Configurable Non-Transparent port  
- Moveable upstream port  
The PEX 8624 provides end-to-end CRC (ECRC) protection and Poison bit  
support to enable designs that require end-to-end data integrity. PLX also  
supports data path parity and memory (RAM) error correction as packets  
pass through the switch.  
Flexible Register & Port Configuration  
- Crosslink port capability  
o Quality of Service (QoS)  
The PEX 8624’s 6 ports can be configured to lane widths of x1, x2, x4, or  
x8. Flexible buffer allocation, along with the device's flexible packet flow  
control, maximizes throughput for applications where more traffic flows in  
the downstream, rather than upstream, direction. Any port can be designated  
as the upstream port, which  
can be changed dynamically.  
The PEX 8624 also provides  
several ways to configure its  
registers. The device can be  
configured through strapping  
pins, I2C interface, host  
software, or an optional  
serial EEPROM. This allows  
for easy debug during the  
development phase,  
- Eight traffic classes per port  
- Weighted round-robin source  
port arbitration  
o Reliability, Availability, Serviceability  
- 3 Hot Plug Ports with native HP Signals  
- All ports hot plug capable thru I2C  
(Hot Plug Controller on every port)  
- ECRC and Poison bit support  
- Data Path parity  
- Memory (RAM) Error Correction  
- INTA# and FATAL_ERR# signals  
- Advanced Error Reporting  
- Port Status bits and GPIO available  
- Per port error diagnostics  
x4  
x8  
PEX 8624  
PEX 8624  
x4 x4 x4 x4  
x8  
5 x4  
x8  
- Performance Monitoring  
• Per port payload & header counters  
performance monitoring  
during the operation phase,  
and driver or software  
PEX 8624  
PEX 8624  
upgrade. Figure 1 shows  
some of the PEX 8624’s  
common port configurations.  
x8 x4 x4  
Figure 1. Common Port Configurations  
x8  
x8  
1234

中文翻译

下载PDF

与PEX8624-AB50BCF相关器件

型号 品牌 获取价格 描述 数据表
PEX8624-BA50BC PLX

获取价格

 		Micro Peripheral IC
PEX8624-BA50BCF PLX

获取价格

 		Micro Peripheral IC
PEX8624-BB50BC PLX

获取价格

 		Micro Peripheral IC
PEX8624-BB50BCF PLX

获取价格

 		PCI Bus Controller, CMOS, PBGA324, 19 X 19 MM, LEAD FREE, FCBGA-324
PEX8625-AA50BCF PLX

获取价格

 		Micro Peripheral IC
PEX8632 PLX

获取价格

 		PCIe Gen2, 5.0GT/s 32-lane, 12-port Switch
PEX8632-AA50BC PLX

获取价格

 		Micro Peripheral IC,
PEX8632-AA50BCF PLX

获取价格

 		Micro Peripheral IC,
PEX8632-AA50BCG PLX

获取价格

 		PCIe Gen2, 5.0GT/s 32-lane, 12-port Switch
PEX8632-AARDK PLX

获取价格

 		PCIe Gen2, 5.0GT/s 32-lane, 12-port Switch

与PEX8624-AB50BCF相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证