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PEX8648-BB50BCF

更新时间： 2024-11-14 06:31:43
品牌 Logo 应用领域
PLX PC外围集成电路
页数 文件大小 规格书
4页 247K
描述
PCI Bus Controller, CMOS, PBGA676, 27 X 27 MM, LEAD FREE, FCBGA-676

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PEX8648-BB50BCF 数据手册

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Version 1.0 2009  
PEX 8648  
PCIe Gen2, 5.0GT/s 48-lane, 12-port PCIe Switch  
Features  
ƒ PEX 8648 Vitals  
o 48-lane, 12-port PCIe Gen2 switch  
- Integrated 5.0 GT/s SerDes  
o 27 x 27mm2, 676-pin FCBGA package  
o Typical Power: 3.7 Watts  
The ExpressLaneTM PEX 8648 device offers PCI Express switching  
capability enabling users to add scalable high bandwidth, non-blocking  
interconnection to a wide variety of applications including servers,  
storage systems, and communications platforms. The PEX 8648 is  
well suited for fan-out, aggregation, and peer-to-peer applications.  
ƒ PEX 8648 Key Features  
o Standards Compliant  
- PCI Express Base Specification, r2.0  
(backwards compatible w/ PCIe r1.0a/1.1)  
- PCI Power Management Spec, r1.2  
- Microsoft Vista Compliant  
- Supports Access Control Services  
- Dynamic link-width control  
- Dynamic SerDes speed control  
o High Performance  
- Non-blocking switch fabric  
- Full line rate on all ports  
- Packet Cut-Thru with 140ns max packet  
latency (x16 to x16)  
- 2KB Max Payload Size  
High Performance & Low Packet Latency  
The PEX 8648 architecture supports packet cut-thru with a maximum  
latency of 140ns (x16 to x16). This, combined with large packet memory  
and non-blocking internal switch architecture, provides full line rate on all  
ports for performance-hungry applications such as servers and switch  
fabrics. The low latency enables applications to achieve high throughput and  
performance. In addition to low latency, the device supports a packet payload  
size of up to 2048 bytes, enabling the user to achieve even higher throughput.  
- Read Pacing (bandwidth throttling)  
- Dual-Cast  
o Flexible Configuration  
Data Integrity  
The PEX 8648 provides end-to-end CRC (ECRC) protection and Poison bit  
support to enable designs that require end-to-end data integrity. PLX also  
supports data path parity and memory (RAM) error correction as packets  
pass through the switch.  
- Ports configurable as x1, x2, x4, x8, x16  
- Registers configurable with strapping  
pins, EEPROM, I2C, or host software  
- Lane and polarity reversal  
- Compatible with PCIe 1.0a PM  
o Dual-Host & Fail-Over Support  
- Configurable Non-Transparent port  
- Moveable upstream port  
Flexible Register & Port Configuration  
The PEX 8648’s 12 ports can be configured to lane widths of x1, x2, x4, x8,  
or x16. Flexible buffer allocation, along with the device's flexible packet  
flow control, maximizes throughput for applications where more traffic  
flows in the downstream, rather than upstream, direction. Any port can be  
designated as the upstream port, which can be changed dynamically. The  
PEX 8648 also provides  
- Crosslink port capability  
o Quality of Service (QoS)  
- Eight traffic classes per port  
- Weighted round-robin source  
port arbitration  
o Reliability, Availability, Serviceability  
- 3 Hot Plug Ports with native HP Signals  
- All ports hot plug capable thru I2C  
(Hot Plug Controller on every port)  
- ECRC and Poison bit support  
- Data Path parity  
several ways to  
x4  
x8  
configure its registers.  
The device can be  
configured through  
strapping pins, I2C  
interface, host  
PEX 8648  
PEX 8648  
- Memory (RAM) Error Correction  
- INTA# and FATAL_ERR# signals  
- Advanced Error Reporting  
software, or an optional  
serial EEPROM. This  
allows for easy debug  
during the development  
phase, performance  
monitoring during the  
operation phase, and  
driver or software  
- Port Status bits and GPIO available  
- Per port error diagnostics  
- Performance Monitoring  
4 x8 2 x4  
x8  
11 x4  
x8  
• Per port payload & header counters  
PEX 8648  
PEX 8648  
upgrade. Figure 1  
shows some of the PEX  
8648’s common port  
configurations.  
2 x8 6x4  
Figure 1. Common Port Configurations  
10 x4  
1234

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