PEX 8724, PCI Express Gen 3 Switch, 24 Lanes, 6 Ports
Highlights
The ExpressLane™ PEX 8724 device offers Multi-Host PCI Express
switching capability enabling users to connect multiple hosts to their
respective endpoints via scalable, high bandwidth, non-blocking
interconnection to a wide variety of applications including servers,
storage, communications, and graphics platforms. The PEX 8724 is
well suited for fan-out, aggregation, and peer-to-peer traffic patterns.
PEX 8724 General Features
o 24-lane, 6-port PCIe Gen 3 switch
- Integrated 8.0 GT/s SerDes
o 19 x 19mm2, 324-pin FCBGA package
o Typical Power: 5.0 Watts
PEX 8724 Key Features
o Standards Compliant
Multi-Host Architecture
- PCI Express Base Specification, r3.0
(compatible w/ PCIe r1.0a/1.1 & 2.0)
- PCI Power Management Spec, r1.2
- Microsoft Vista Compliant
- Supports Access Control Services
- Dynamic link-width control
- Dynamic SerDes speed control
o High Performance
The PEX 8724 employs an enhanced version of PLX’s field tested PEX 8624
PCIe switch architecture, which allows users to configure the device in legacy
single-host mode or multi-host mode with up to four host ports capable of 1+1
(one active & one backup) or N+1 (N active & one backup) host failover. This
powerful architectural enhancement enables users to build PCIe based systems
to support high-availability, failover, redundant, or clustered systems.
♦
performancePAK
9 Read Pacing (bandwidth throttling)
9 Multicast
High Performance & Low Packet Latency
The PEX 8724 architecture supports packet cut-thru with a maximum
latency of 106ns (x8 to x8). This, combined with large packet memory,
flexible common buffer/FC credit pool and non-blocking internal switch
architecture, provides full line rate on all ports for performance-hungry
applications such as servers and switch fabrics. The low latency enables
applications to achieve high throughput and performance. In addition to low
latency, the device supports a packet payload size of up to 2048 bytes,
enabling the user to achieve even higher throughput.
9 Dynamic Buffer/FC Credit Pool
- Non-blocking switch fabric
- Full line rate on all ports
- Packet Cut-Thru with 106ns max packet
latency (x8 to x8)
- 2KB Max Payload Size
o Flexible Configuration
- Ports configurable as x1, x2, x4, x8
- Registers configurable with strapping
pins, EEPROM, I2C, or host software
- Lane and polarity reversal
- Compatible with PCIe 1.0a PM
o Multi-Host & Fail-Over Support
- Configurable Non-Transparent (NT) port
- Failover with NT port
- Up to 4 upstream/Host ports with 1+1 or
N+1 failover to other upstream ports
o Quality of Service (QoS)
- Eight traffic classes per port
- Weighted round-robin source
port arbitration
Data Integrity
The PEX 8724 provides end-to-end CRC (ECRC) protection and Poison bit
support to enable designs that require end-to-end data integrity. PLX also
supports data path parity and memory (RAM) error correction circuitry
throughout the internal data paths as packets pass through the switch.
Flexible Configuration
The PEX 8724’s 6 ports can be
x4
x8
configured to lane widths of x1,
x2, x4, or x8. Flexible buffer
allocation, along with the device's
flexible packet flow control,
o Reliability, Availability, Serviceability
♦ visionPAK
PEX 8724
PEX 8724
9 Per Port Performance Monitoring
Per port payload & header counters
9 SerDes Eye Capture
maximizes
throughput
for
9 PCIe Packet Generator
applications where more traffic
flows in the downstream, rather
than upstream, direction. Any
port can be designated as the
upstream port, which can be
changed dynamically. Figure 1
shows some of the PEX 8724’s
common port configurations in
legacy Single-Host mode.
x4 x4 x4 x4
x8
5 x4
x8
9 Error Injection and Loopback
- 3 Hot Plug Ports with native HP Signals
- All ports hot plug capable thru I2C
(Hot Plug Controller on every port)
- ECRC and Poison bit support
- Data Path parity
- Memory (RAM) Error Correction
- INTA# and FATAL_ERR# signals
- Advanced Error Reporting
PEX 8724
PEX 8724
x8 x4 x4
x8
x8
- Port Status bits and GPIO available
• Per port error diagnostics
- JTAG AC/DC boundary scan
Figure 1. Common Port Configurations
© PLX Technology, www.plxtech.com
Page 1 of 5
10/7/2010, Version 1.0
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