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PEX9733-AA80BCG PDF预览

PEX9733-AA80BCG

更新时间: 2024-11-14 00:45:35
品牌 Logo 应用领域
安华高科 - AVAGO PC
页数 文件大小 规格书
3页 471K
描述
Managed PCI Express Switches Based on ExpressFabric Technology

PEX9733-AA80BCG 数据手册

 浏览型号PEX9733-AA80BCG的Datasheet PDF文件第2页浏览型号PEX9733-AA80BCG的Datasheet PDF文件第3页 
Product Brief  
PEX9700 Series Switch Chips  
Managed PCI Express Switches Based on ExpressFabric® Technology  
Converge Servers and IO controllers with PCIe  
General Features  
n■  
n
Create cost-effective high-availability hyperscale systems  
by enabling communication between in-rack hosts and  
endpoints using PCIe  
State-of-the-art switch fabric  
– Sharing I/Os among multiple hosts  
– Host-to-host DMA  
n
Simplify connectivity while providing the highest PCIe  
switching performance available for data center servers,  
storage, and networks  
– Low latency TWC  
n■  
Any port can be a host port or  
Downstream (device) Port  
n
n
Reduce latency, system complexity, and power consumption  
by up to 50% in data-intensive environments  
n■  
Works with standard PCIe end-points  
and hosts – and software, as well as  
with existing application software  
Take advantage of industry-first features for most demanding  
hyper-converged, NVMe and rack scale systems  
n■  
MSI-X support  
n■  
Allows flexible fabric topologies  
Avago PEX9700 switches allow customers to build high performance,  
low latency, scalable, cost-effective PCI Express-based fabrics. The  
Key Advantages  
n■  
switches enable I/O sharing with standard SR-IOV or multifunction capability, allowing multiple hosts  
or Nodes to reside on a single PCIe-based network. Hosts communicate through Ethernet-like DMA  
(NIC DMA) with other hosts and end-points using application software. Hosts may also communicate  
using Tunneled Window Connection (TWC), a special low latency host-to-host communication  
capability for short packets.  
PCI Express Switches  
–12 to 97 Lanes with Integrated  
on-chip SerDes  
–5 to 25 Independent ports  
–Designate any Port as the  
Upstream Port  
Shared I/O Using Standards  
– Low-power SerDes (under 90 mW  
per Lane)  
PEX9700 switches allow the Virtual Functions (VFs) of SRIOV endpoints (such as an Avago  
MegaRAID® SAS controller) to be shared and assigned to multiple hosts concurrently. Each host  
can enumerate its assigned functions using standard BIOS and OS software and use them with  
unmodified vendor-supplied drivers. The use of standard system software minimizes software  
support costs.  
– Device-Specific Relaxed Ordering  
– Port configuration  
– Dedicated management port  
for mCPU  
– x4, x8, or x16, depending on Port  
configuration; x4 can down-train to  
x1 and x2 width  
General Purpose Host-to-Host DMA  
Ethernet is used almost universally for server to server communications. PEX9700 switches  
contain a virtual Ethernet NIC at each host port that allows Ethernet to be tunneled transparently  
through the fabric to any and all servers that are connected. Internal Ethernet communications  
using virtual Ethernet NICs and NIC DMA are complemented by the ability to share a physical  
SRIOV NIC, thus providing compatibility with the vast library of applications that leverage  
Ethernet communications.  
– Configurable through serial EEPROM,  
I2C, SMBus, and/or Host port  
n■  
Standards Compliant  
– PCI Express Base Specification, r3.1  
(backward compatible w/ PCIe r2.0,  
& r1.0a/1.1)  
Software-Defined Fabric  
– PCI Power Management Spec, r1.2  
n■  
High Performance  
The switches are built on a hybrid hardware/software platform that offers high configurability and  
flexibility in regards to the number of hosts, end-points, and PCIe slots. The critical pathways have  
direct hardware support, enabling the fabric to offer non-blocking, line speed performance with  
features such as I/O sharing and DMA. The solution is completed by management processor that  
communicates with platform management via API and/or CLI. The solution offers an innovative  
approach to setup and control, making use of an off-chip management CPU (mCPU) to initialize  
the PEX9700 switch, configure the routing tables, handle errors, Hot-Plug events, and enable the  
solution to extend the capabilities without modifying the system software.  
– Full line rate on all ports  
– Cut-Thru packet latency of less than  
150ns (x16 to x16)  
– 2KB Max Payload Size  
– Multicast through DMA  

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