PEX 8664, PCI Express Gen 2 Switch, 64 Lanes, 16 Ports
The ExpressLaneTM PEX 8664 device offers Multi-Host PCI Express
switching capability enabling users to connect multiple hosts to their
respective endpoints via scalable, high bandwidth, non-blocking
interconnection to a wide variety of applications including servers,
storage systems, and communications platforms. The PEX 8664 is
well suited for fan-out, aggregation, and peer-to-peer applications.
Features
PEX 8664 General Features
o 64-lane, 16-port PCIe Gen2 switch
- Integrated 5.0 GT/s SerDes
o 35 x 35mm2, 1156-ball FCBGA package
o Typical Power: 7.9 Watts
PEX 8664 Key Features
o Standards Compliant
Multi-Host Architecture
The PEX 8664 employs an enhanced version of PLX’s field tested PEX 8648
- PCI Express Base Specification, r2.0
(backwards compatible w/ PCIe r1.0a/1.1)
- PCI Power Management Spec, r1.2
- Microsoft Vista Compliant
- Supports Access Control Services
- Dynamic link-width control
- Dynamic SerDes speed control
o High Performance
PCIe switch architecture, which allows users to configure the device in
legacy single-host mode or multi-host mode with up to five host ports
capable of 1+1 (one active & one backup) or N+1 (N active & one backup)
host failover. This powerful architectural enhancement enables users to build
PCIe based systems to support high-availability, failover, redundant and
clustered systems.
♦ performancePAK
9 Read Pacing (bandwidth throttling)
9 Multicast
9 Dynamic Buffer/FC Credit Pool
- Non-blocking switch fabric
- Full line rate on all ports
- Packet Cut-Thru with 176ns max packet
latency (x16 to x16)
- 2KB Max Payload Size
High Performance & Low Packet Latency
The PEX 8664 architecture supports packet cut-thru with a maximum
latency of 176ns (x16 to x16). This, combined with large packet memory,
flexible common buffer/FC credit pool and non-blocking internal switch
architecture, provides full line rate on all ports for performance-hungry
applications such as servers and switch fabrics. The low latency enables
applications to achieve high throughput and performance. In addition to low
latency, the device supports a packet payload size of up to 2048 bytes,
enabling the user to achieve even higher throughput.
o Flexible Configuration
- Ports configurable as x1, x2, x4, x8, x16
- Registers configurable with strapping
pins, EEPROM, I2C, or host software
- Lane and polarity reversal
- Compatible with PCIe 1.0a PM
o Multi-Host & Fail-Over Support
- Configurable Non-Transparent (NT) port
- Failover with NT port
- Up to Five upstream/Host ports with 1+1
or N+1 failover to other upstream ports
o Quality of Service (QoS)
Data Integrity
The PEX 8664 provides end-to-end CRC (ECRC) protection and Poison bit
support to enable designs that require end-to-end data integrity. PLX also
supports data path parity and memory (RAM) error correction circuitry
throughout the internal data paths as packets pass through the switch.
- Eight traffic classes per port
- Weighted round-robin source
port arbitration
o Reliability, Availability, Serviceability
♦ visionPAK
9 Per Port Performance Monitoring
Per port payload & header counters
9 SerDes Eye Capture
9 Error Injection and Loopback
- 4 Hot Plug Ports with native HP Signals
- All ports hot plug capable thru I2C
(Hot Plug Controller on every port)
- ECRC and Poison bit support
- Data Path parity
Flexible Configuration
x4
x8
The PEX 8664’s 16 ports can be
configured to lane widths of x1, x2, x4,
x8, or x16. Flexible buffer allocation,
along with the device's flexible packet
flow control, maximizes throughput
for applications where more traffic
flows in the downstream, rather than
upstream, direction. Any port can be
designated as the upstream port, which
can be changed dynamically. Figure 1
shows some of the PEX 8664’s
PEX 8664
PEX 8664
5 x8 4 x4
x16
15 x4
x8
PEX 8664
PEX 8664
- Memory (RAM) Error Correction
- INTA# and FATAL_ERR# signals
- Advanced Error Reporting
- Port Status bits and GPIO available
- Per port error diagnostics
common port configurations in legacy
Single-Host mode.
2 x8 10 x4
Figure 1. Common Port Configurations
6 x8
- JTAG AC/DC boundary scan
© PLX Technology, www.plxtech.com
Page 1 of 1
5/14/2009, Version 1.1
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