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PEX8612-BB50BC PDF预览

PEX8612-BB50BC

更新时间： 2024-11-30 15:47:47
品牌 Logo 应用领域
PLX PC外围集成电路
页数 文件大小 规格书
4页 161K
描述
PCI Bus Controller, CMOS, 19 X 19 MM, LEAD FREE, FCBGA-324

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PEX8612-BB50BC 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：BGA,针数：324
Reach Compliance Code：unknown风险等级：5.5
地址总线宽度：总线兼容性：I2C
外部数据总线宽度：JESD-30 代码：S-XBGA-B324
JESD-609代码：e0端子数量：324
封装主体材料：UNSPECIFIED封装代码：BGA
封装形状：SQUARE封装形式：GRID ARRAY
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
表面贴装：YES技术：CMOS
端子面层：TIN LEAD端子形式：BALL
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
uPs/uCs/外围集成电路类型：BUS CONTROLLER, PCIBase Number Matches：1

PEX8612-BB50BC 数据手册

 浏览型号PEX8612-BB50BC的Datasheet PDF文件第2页浏览型号PEX8612-BB50BC的Datasheet PDF文件第3页浏览型号PEX8612-BB50BC的Datasheet PDF文件第4页 
Version 0.96 2008  
Features  
PEX 8612  
PCIe Gen2, 5.0GT/s 12-lane, 3-port Switch  
ƒ PEX 8612 General Features  
o 12-lane, 3-port PCIe Gen2 switch  
- Integrated 5.0 GT/s SerDes  
o 19 x 19mm2, 324-pin FCBGA package  
o Typical Power: 1.5 Watts  
The ExpressLaneTM PEX 8612 device offers PCI Express switching  
capability enabling users to add scalable high bandwidth, non-blocking  
interconnection to a wide variety of applications including  
workstations, storage systems, communications platforms,  
embedded systems, and intelligent I/O modules. The PEX 8612 is  
well suited for fan-out, aggregation, and peer-to-peer applications.  
ƒ PEX 8612 Key Features  
o Standards Compliant  
- PCI Express Base Specification, r2.0  
(backwards compatible w/ PCIe r1.0a/1.1)  
- PCI Power Management Spec, r1.2  
- Microsoft Vista Compliant  
- Supports Access Control Services  
- Dynamic link-width control  
- Dynamic SerDes speed control  
o High Performance  
- Non-blocking switch fabric  
- Full line rate on all ports  
- Packet Cut-Thru with 170ns max packet  
latency (x4 to x4)  
- 2KB Max Payload Size  
High Performance & Low Packet Latency  
The PEX 8612 architecture supports packet cut-thru with a maximum  
latency of 170ns (x4 to x4). This, combined with large packet memory and  
non-blocking internal switch architecture, provides full line rate on all ports  
for performance-hungry applications such as servers and switch fabrics.  
The low latency enables applications to achieve high throughput and  
performance. In addition to low latency, the device supports a max payload  
size of 2048 bytes, enabling the user to achieve even higher throughput.  
- Read Pacing (bandwidth throttling)  
- Dual-Cast  
o Flexible Configuration  
- Ports configurable as x1, x2, x4  
- Registers configurable with strapping  
pins, EEPROM, I2C, or host software  
- Lane and polarity reversal  
- Compatible with PCIe 1.0a PM  
o Dual-Host & Fail-Over Support  
- Configurable Non-Transparent port  
- Moveable upstream port  
Data Integrity  
The PEX 8612 provides end-to-end CRC (ECRC) protection and Poison bit  
support to enable designs that require end-to-end data integrity. PLX also  
supports data path parity and memory (RAM) error correction as packets  
pass through the switch.  
- Crosslink port capability  
o Quality of Service (QoS)  
Flexible Register & Port Configuration  
- Eight traffic classes per port  
- Weighted round-robin source  
port arbitration  
o Reliability, Availability, Serviceability  
- 2 Hot Plug Ports with native HP Signals  
- All ports hot plug capable thru I2C  
(Hot Plug Controller on every port)  
- ECRC and Poison bit support  
- Data Path parity  
- Memory (RAM) Error Correction  
- INTA# and FATAL_ERR# signals  
- Advanced Error Reporting  
- Port Status bits and GPIO available  
- Per port error diagnostics  
The PEX 8612’s 3 ports can be configured to lane widths of x1, x2, or x4.  
Flexible buffer allocation, along with the device's flexible packet flow  
control, maximizes throughput for applications where more traffic flows in  
the downstream, rather than upstream, direction. Any port can be designated  
as the upstream port, which  
x4  
x4  
can be changed dynamically.  
The PEX 8612 also provides  
several ways to configure its  
registers. The device can be  
configured through  
PEX 8612  
PEX 8612  
strapping pins, I2C  
- Performance Monitoring  
• Per port payload & header counters  
- JTAG AC/DC boundary scan  
interface, host software, or  
an optional serial EEPROM.  
This allows for easy debug  
during the development  
phase, performance  
x4  
x4  
x2  
x2  
x4  
NT  
monitoring during the  
PEX 8612  
operation phase, and driver  
or software upgrade. Figure  
1 shows some of the  
PEX 8612’s common port  
configurations.  
x4  
Figure 1. Common Port Configurations  
Preliminary - PLX Confidential  
1234

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