PEX8613-BA50BCG

更新时间： 2024-09-25 06:00:19

品牌	Logo	应用领域
PLX		总线控制器微控制器和处理器外围集成电路 PC
页数	文件大小	规格书
4页	188K
描述
PCIe Gen 2, 5.0GT/s 12-lane, 3-port Switch

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技术参数
数据手册

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PEX8613-BA50BCG 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Transferred	零件包装代码：	BGA
包装说明：	BGA,	针数：	324
Reach Compliance Code：	unknown	风险等级：	5.69
Is Samacsys：	N	总线兼容性：	I2C
JESD-30 代码：	S-PBGA-B324	端子数量：	324
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装形状：	SQUARE	封装形式：	GRID ARRAY
峰值回流温度（摄氏度）：	NOT SPECIFIED	表面贴装：	YES
技术：	CMOS	端子形式：	BALL
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
uPs/uCs/外围集成电路类型：	BUS CONTROLLER, PCI	Base Number Matches：	1

PEX8613-BA50BCG 数据手册

Version 1.1 2009

Features

PEX 8613

PCIe Gen 2, 5.0GT/s 12-lane, 3-port Switch

PEX 8613 General Features

o 12-lane, 3-port PCIe Gen 2 switch

- Integrated 5.0 GT/s SerDes

o 19 x 19mm², 324-pin PBGA package

o Typical Power: 1.74 Watts

The ExpressLane^TMPEX 8613 device offers PCI Express switching

capability enabling users to add scalable high bandwidth, non-blocking

interconnection to a wide variety of applications including

workstations, storage systems, communications platforms,

embedded systems, and intelligent I/O modules. The PEX 8613 is

well suited for fan-out, aggregation, and peer-to-peer applications.

PEX 8613 Key Features

o Standards Compliant

- PCI Express Base Specification, r2.0

(backwards compatible w/ PCIe r1.0a/1.1)

- PCI Power Management Spec, r1.2

- Microsoft Vista Compliant

- Supports Access Control Services

- Dynamic link-width control

- Dynamic SerDes speed control

o High Performance

- Non-blocking switch fabric

- Full line rate on all ports

- Packet Cut-Thru with 140ns max packet

latency (x4 to x4)

- 2KB Max Payload Size

- Read Pacing (bandwidth throttling)

- Dual cast

o Flexible Configuration

- Registers configurable with strapping

pins, EEPROM, I²C, or host software

- Lane and polarity reversal

- Compatible with PCIe 1.0a PM

o Dual-Host & Fail-Over Support

- Configurable Non-Transparent port

- Moveable upstream port

High Performance & Low Packet Latency

The PEX 8613 architecture supports packet cut-thru with a maximum

latency of 140ns (x4 to x4). This, combined with large packet memory and

non-blocking internal switch architecture, provides full line rate on all ports

for performance-hungry applications such as servers and switch fabrics.

The low latency enables applications to achieve high throughput and

performance. In addition to low latency, the device supports a max payload

size of 2048 bytes, enabling the user to achieve even higher throughput.

Data Integrity

The PEX 8613 provides end-to-end CRC (ECRC) protection and Poison bit

support to enable designs that require end-to-end data integrity. PLX also

supports data path parity and memory (RAM) error correction as packets

pass through the switch.

- Crosslink port capability

o Dual-Clock Domain

- SSC clock isolation

o Quality of Service (QoS)

- Two Virtual Channels

Flexible Register & Port Configuration

The PEX 8613’s 3 ports can achieve link up to lane widths of x1, x2, or x4.

Flexible buffer allocation, along with the device's flexible packet flow

control, maximizes throughput for applications where more traffic flows in

the downstream, rather than upstream, direction. Any port can be designated

as the upstream port, which

- Eight traffic classes per port

- Weighted round-robin source

port arbitration

o Reliability, Availability, Serviceability

- All ports Hot-Plug capable thru I²C

(Hot-Plug Controller on every port)

- ECRC and Poison bit support

- Data Path parity

- Memory (RAM) Error Correction

- INTA# and FATAL_ERR# signals

- Advanced Error Reporting

- Port Status bits and GPIO available

- Per port error diagnostics

can be changed dynamically.

The PEX 8613 also provides

several ways to configure its

registers. The device can be

configured through

PEX 8613

strapping pins, I²C

interface, host software, or

an optional serial EEPROM.

This allows for easy debug

during the development

phase, performance

- Performance Monitoring

• Per port payload & header counters

- JTAG AC/DC boundary scan

PEX 8613

monitoring during the

operation phase, and driver

or software upgrade. Figure

1 shows some of the

PEX 8613’s common port

configurations.

Figure 1. Common Port Configurations

12 3 4

中文翻译

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与PEX8613-BA50BCG相关器件

型号	品牌	获取价格	描述	数据表
PEX8613BA-AIC4U4DRDK	PLX	获取价格	PCIe Gen 2, 5.0GT/s 12-lane, 3-port Switch
PEX8614	PLX	获取价格	Flexible & Versatile 12-lane 12-port PCI Express Switch
PEX8614-AA50BC	PLX	获取价格	Flexible & Versatile 12-lane 12-port PCI Express Switch
PEX8614-AA50BCG	PLX	获取价格	Flexible & Versatile 12-lane 12-port PCI Express Switch
PEX8614AA-AIC4U4DRDK	PLX	获取价格	Flexible & Versatile 12-lane 12-port PCI Express Switch
PEX8614AA-BB4U1DRDK	PLX	获取价格	Flexible & Versatile 12-lane 12-port PCI Express Switch
PEX8615	PLX	获取价格	Flexible & Versatile 12-lane 12-port PCI Express Switch
PEX8615-BA50BC	PLX	获取价格	Flexible & Versatile 12-lane 12-port PCI Express Switch
PEX8615-BA50BCG	PLX	获取价格	Flexible & Versatile 12-lane 12-port PCI Express Switch
PEX8615-BA50BIG	PLX	获取价格	Micro Peripheral IC,

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