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PEX8617BA-AIC4U4DRDK PDF预览

PEX8617BA-AIC4U4DRDK

更新时间: 2024-11-30 06:00:19
品牌 Logo 应用领域
PLX PC
页数 文件大小 规格书
4页 370K
描述
PCIe Gen 2, 5.0GT/s 16-lane, 4-port Switch

PEX8617BA-AIC4U4DRDK 数据手册

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Version 1.1 2009  
Features  
PEX 8617  
ƒ PEX 8617 General Features  
o 16-lane, 4-port PCIe Gen 2 switch  
- Integrated 5.0 GT/s SerDes  
o 19 x 19mm2, 324-pin PBGA package  
o Typical Power: 1.93 Watts  
PCIe Gen 2, 5.0GT/s 16-lane, 4-port Switch  
The ExpressLaneTM PEX 8617 device offers PCI Express switching  
capability enabling users to add scalable high bandwidth, non-blocking  
interconnection to a wide variety of applications including  
workstations, storage systems, communications platforms,  
embedded systems, and intelligent I/O modules. The PEX 8617 is  
well suited for fan-out, aggregation, and peer-to-peer applications.  
ƒ PEX 8617 Key Features  
o Standards Compliant  
- PCI Express Base Specification, r2.0  
(backwards compatible w/ PCIe r1.0a/1.1)  
- PCI Power Management Spec, r1.2  
- Microsoft Vista Compliant  
- Supports Access Control Services  
- Dynamic link-width control  
- Dynamic SerDes speed control  
o High Performance  
- Non-blocking switch fabric  
- Full line rate on all ports  
- Packet Cut-Thru with 140ns max packet  
latency (x4 to x4)  
- 2KB Max Payload Size  
High Performance & Low Packet Latency  
The PEX 8617 architecture supports packet cut-thru with a maximum  
latency of 140ns (x4 to x4). This, combined with large packet memory and  
non-blocking internal switch architecture, provides full line rate on all ports  
for performance-hungry applications such as servers and switch fabrics.  
The low latency enables applications to achieve high throughput and  
performance. In addition to low latency, the device supports a max payload  
size of 2048 bytes, enabling the user to achieve even higher throughput.  
- Read Pacing (bandwidth throttling)  
- Dual Cast  
o Flexible Configuration  
- Ports configurable as x1, x2, x4, x8  
- Registers configurable with strapping  
pins, EEPROM, I2C, or host software  
- Lane and polarity reversal  
- Compatible with PCIe 1.0a PM  
o Dual-Host & Fail-Over Support  
- Configurable Non-Transparent port  
- Moveable upstream port  
Data Integrity  
The PEX 8617 provides end-to-end CRC (ECRC) protection and Poison bit  
support to enable designs that require end-to-end data integrity. PLX also  
supports data path parity and memory (RAM) error correction as packets  
pass through the switch.  
- Crosslink port capability  
- SSC Isolation  
o Quality of Service (QoS)  
Flexible Register & Port Configuration  
The PEX 8617’s 4 ports can be configured to lane widths of x1, x2, x4, or  
x8. Flexible buffer allocation, along with the device's flexible packet flow  
control, maximizes throughput for applications where more traffic flows in  
the downstream, rather than upstream, direction. Any port can be designated  
as the upstream port, which can be changed dynamically. The PEX 8617 also  
provides several ways to  
- Two Virtual Channels  
- Eight traffic classes per port  
- Weighted round-robin source  
port arbitration  
o Reliability, Availability, Serviceability  
- 2 Hot-Plug Ports with native HP Signals  
- All ports Hot-Plug capable thru I2C  
(Hot-Plug Controller on every port)  
- ECRC and Poison bit support  
- Data Path parity  
configure its registers.  
x8  
x4  
The device can be  
configured through  
strapping pins, I2C  
interface, host software,  
or an optional serial  
EEPROM. This allows  
for easy debug during  
the development phase,  
performance monitoring  
during the operation  
phase, and driver or  
software upgrade.  
- Memory (RAM) Error Correction  
- INTA# and FATAL_ERR# signals  
- Advanced Error Reporting  
- Port Status bits and GPIO available  
- Per port error diagnostics  
- Performance Monitoring  
Per port payload & header counters  
- JTAG AC/DC boundary scan  
PEX 8617  
PEX 8617  
x4  
x4  
x8  
x4 x4 x4  
x4  
NT  
PEX 8617  
PEX 8617  
Figure 1 shows some of  
the PEX 8617’s  
common port  
x8  
x4 x2 x2  
Figure 1. Common Port Configurations  
configurations.  

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PCI Bus Controller, CMOS, PBGA324, 19 X 19 MM, LEAD FREE, HSBGA-324