Product Specification
PE42510A
SPDT High Power UltraCMOS™
RF Switch 30 - 2000 MHz
Product Description
Features
The following specification defines an SPDT (single pole
double throw) switch for use in cellular and other wireless
applications. The PE42510A uses Peregrine’s UltraCMOS™
process and it also features HaRP™ technology
enhancements to deliver high linearity and exceptional
harmonics performance. HaRP™ technology is an innovative
feature of the UltraCMOS™ process providing upgraded
linearity performance.
•
•
•
No blocking capacitors required
50 Watt P1dB compression point
10 Watts <8:1 VSWR (Normal
Operation)
•
•
•
•
•
29 dB Isolation @800 MHz
< 0.3 dB Insertion Loss at 800 MHz
2fo and 3fo < -84 dBc @ 42.5 dBm
ESD rugged to 2.0 kV HBM
The PE42510A is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
32-lead 5x5 mm QFN package
Figure 1. Functional Diagram
Figure 2. Package Type
32-lead 5x5 mm QFN
RFC
RF1
RF2
CMOS
Control Driver
and ESD
CTRL
Table 1. Electrical Specifications @ 25 °C, VDD = 3.3 V (ZS = ZL = 50 Ω) unless otherwise noted
Parameter
Conditions
Min
Typ
Max
Units
30 MHz ≤ 1 GHz
1 GHz < 2 GHz
0.4
0.5
0.6
0.7
dB
dB
RF Insertion Loss
0.1 dB Input Compression Point
800 MHz, 50% duty cycle
800 MHz
45.4
29
dBm
dB
Isolation (Supply Biased): RF to RFC
25
5
Unbiased Isolation: RF - RFC, VDD, V1=0 V
RF (Active Port) Return Loss
27 dBm, 800 MHz
dB
dB
15
22
2nd Harmonic
3rd Harmonic
800 MHz @ +42.5 dBm
-84
-81
0.5
dBc
Switching Time
50% of CTRL to 10/90% of RF
No RF applied
0.04
ms
Lifetime switch cycles
10^10
cycles
Note: The device was matched with 1.6 nH inductance per RF port
Document No. 70-0266-01 │ www.psemi.com
©2008 Peregrine Semiconductor Corp. All rights reserved.
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