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PDM41257SA12SOTR PDF预览

PDM41257SA12SOTR

更新时间: 2024-09-17 23:27:11
品牌 Logo 应用领域
其他 - ETC 静态存储器
页数 文件大小 规格书
7页 295K
描述
x1 SRAM

PDM41257SA12SOTR 数据手册

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PDM41257  
256K Static RAM  
256K x 1-Bit  
1
2
Description  
Features  
The PDM41257 is a high-performance CMOS static  
RAM organized as 262,144 x 1 bit. Writing to this  
device is accomplished when the write enable (WE)  
and the chip enable (CE) inputs are both LOW.  
Reading is accomplished when WE remains HIGH  
and CE goes LOW.  
High-speed access times  
Com’l: 7, 8, 10, 12 and 15 ns  
Industrial: 8, 10, 12 and 15 ns  
Low power operation (typical)  
- PDM41257SA  
Active: 400 mW  
Standby: 150 mW  
- PDM41257LA  
Active: 350 mW  
Standby: 25 mW  
The PDM41257 operates from a single +5V power  
supply and all the inputs and outputs are fully TTL-  
compatible. The PDM41257 comes in two versions,  
the standard power version PDM41257SA and a low  
power version the PDM41257LA. The two versions  
are functionally the same and only differ in their  
power consumption.  
4
Single +5V (±10%) power supply  
TTL compatible inputs and outputs  
Packages  
5
The PDM41257 is available in a 24-pin 300-mil  
plastic SOJ for surface mount applications.  
Plastic SOJ (300 mil) - SO  
6
7
Functional Block Diagram  
A0  
8
Memory  
Matrix  
Addresses  
Decoder  
A17  
9
• • • • •  
Column I/O  
DIN  
DOUT  
10  
11  
12  
CE  
WE  
Rev. 2.2 - 4/27/98  
1

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