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PDM41024LA12TI PDF预览

PDM41024LA12TI

更新时间: 2024-10-28 04:54:03
品牌 Logo 应用领域
其他 - ETC 内存集成电路静态存储器光电二极管
页数 文件大小 规格书
8页 295K
描述
1 Megabit Static RAM 128K x 8-Bit

PDM41024LA12TI 数据手册

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PDM41024  
Write Cycle No. 3 (Chip Enable Controlled)  
t
WC  
1
2
ADDR  
t
t
AH  
AW  
t
t
AS  
CW  
CE2  
CE1  
t
3
WP1  
WE  
t
t
DH  
DS  
D
DATA VALID  
IN  
HIGH-Z  
D
OUT  
NOTE: Output Enable (OE) is inactive (high)  
5
6
AC Electrical Characteristics  
(7)  
(7)  
Description  
-10  
-12  
-15  
WRITE Cycle  
Sym  
Min. Max. Min. Max. Min. Max. Units  
7
WRITE cycle time  
t
t
10  
10  
10  
0
12  
10  
10  
0
15  
11  
11  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
Chip enable active time  
Address valid to end of write  
Address setup time  
CW  
t
AW  
8
t
AS  
AH  
Address hold from end of write  
Write pulse width  
t
0
0
0
t
8
8
11  
12  
7
WP1  
WP2  
Write pulse width  
t
8
8
9
Data setup time  
t
7
7
DS  
Data hold time  
t
0
0
0
DH  
(1,3)  
(1,3)  
Write disable to output in low Z  
t
0
0
0
LZWE  
HZWE  
10  
11  
12  
Write enable to output in high Z  
t
7
7
7
SHADED AREA = PRELIMINARY DATA  
Notes referenced are after Data Retention Table  
Rev. 3.3 - 4/09/98  
7

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