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PDM41024LA12TSOTY PDF预览

PDM41024LA12TSOTY

更新时间: 2024-11-25 20:13:31
品牌 Logo 应用领域
IXYS 静态存储器光电二极管
页数 文件大小 规格书
8页 235K
描述
Standard SRAM, 128KX8, 12ns, CMOS, PDSO32

PDM41024LA12TSOTY 技术参数

是否无铅: 不含铅是否Rohs认证: 不符合
生命周期:Obsolete包装说明:SOJ, SOJ32,.34
Reach Compliance Code:compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.11
最长访问时间:12 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-J32内存密度:1048576 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
功能数量:1端子数量:32
字数:131072 words字数代码:128000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:128KX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOJ封装等效代码:SOJ32,.34
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
最大待机电流:0.0005 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.21 mA
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:J BEND端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

PDM41024LA12TSOTY 数据手册

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PDM41024  
1 Megabit Static RAM  
128K x 8-Bit  
1
2
Description  
Features  
The PDM41024 is a high-performance CMOS static  
RAM organized as 131,072 x 8 bits. Writing is  
accomplished when the write enable (WE) and the  
chip enable (CE1) inputs are both LOW and CE2 is  
HIGH. Reading is accomplished when WE and CE2  
remain HIGH and CE1 and OE are both LOW.  
High-speed access times  
Com’l: 10, 12 and 15 ns  
Ind’l: 12 and 15 ns  
Low power operation (typical)  
- PDM41024SA  
3
Active: 450 mW  
Standby: 50 mW  
- PDM41024LA  
Active: 400 mW  
The PDM41024 operates from a single +5V power  
supply and all the inputs and outputs are fully TTL-  
compatible. The PDM41024 comes in two versions:  
the standard power version (SA) and the low power  
version (LA). The two versions are functionally the  
same and differ only in their power consumption.  
Standby: 25mW  
Single +5V (±10%) power supply  
TTL-compatible inputs and outputs  
Packages  
The PDM41024 is available in a 32-pin plastic TSOP  
(I), and a 300-mil and 400-mil plastic SOJ.  
5
Plastic SOJ (300 mil) - TSO  
Plastic SOJ (400 mil) - SO  
Plastic TSOP (I)- T  
6
Functional Block Diagram  
7
A0  
Decoder  
Memory  
8
Addresses  
Matrix  
A16  
9
• • • • •  
Column I/O  
I/O0  
Input  
Data  
Control  
10  
11  
12  
I/O7  
CE1  
CE2  
WE  
OE  
Control  
Rev. 3.3 - 4/09/98  
1

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