Datasheet > PDM41024LA15TSOITR

PDM41024LA15TSOITR

更新时间： 2024-11-25 03:45:11

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
8页	295K
描述
1 Megabit Static RAM 128K x 8-Bit

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PDM41024LA15TSOITR 数据手册

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PDM41024

1 Megabit Static RAM

128K x 8-Bit

Description

Features

The PDM41024 is a high-performance CMOS static

RAM organized as 131,072 x 8 bits. Writing is

accomplished when the write enable (WE) and the

chip enable (CE1) inputs are both LOW and CE2 is

HIGH. Reading is accomplished when WE and CE2

remain HIGH and CE1 and OE are both LOW.

■ High-speed access times

Com’l: 10, 12 and 15 ns

Ind’l: 12 and 15 ns

■ Low power operation (typical)

- PDM41024SA

Active: 450 mW

Standby: 50 mW

- PDM41024LA

Active: 400 mW

The PDM41024 operates from a single +5V power

supply and all the inputs and outputs are fully TTL-

compatible. The PDM41024 comes in two versions:

the standard power version (SA) and the low power

version (LA). The two versions are functionally the

same and differ only in their power consumption.

Standby: 25mW

■ Single +5V (±10%) power supply

■ TTL-compatible inputs and outputs

■ Packages

The PDM41024 is available in a 32-pin plastic TSOP

(I), and a 300-mil and 400-mil plastic SOJ.

Plastic SOJ (300 mil) - TSO

Plastic SOJ (400 mil) - SO

Plastic TSOP (I)- T

Functional Block Diagram

A₀

Decoder

Memory

•

Addresses

Matrix

•

A₁₆

• • • • •

Column I/O

I/O₀

Input

Data

Control

•

I/O₇

•

CE1

CE2

Control

Rev. 3.3 - 4/09/98

12 3 4 5 6 7 8

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