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PDM41024LA12TI PDF预览

PDM41024LA12TI

更新时间: 2024-10-28 04:54:03
品牌 Logo 应用领域
其他 - ETC 内存集成电路静态存储器光电二极管
页数 文件大小 规格书
8页 295K
描述
1 Megabit Static RAM 128K x 8-Bit

PDM41024LA12TI 数据手册

 浏览型号PDM41024LA12TI的Datasheet PDF文件第2页浏览型号PDM41024LA12TI的Datasheet PDF文件第3页浏览型号PDM41024LA12TI的Datasheet PDF文件第4页浏览型号PDM41024LA12TI的Datasheet PDF文件第6页浏览型号PDM41024LA12TI的Datasheet PDF文件第7页浏览型号PDM41024LA12TI的Datasheet PDF文件第8页 
PDM41024  
(4, 5)  
Read Cycle No. 1  
1
2
t
RC  
ADDR  
t
AA  
t
OH  
D
PREVIOUS DATA VALID  
DATA VALID  
OUT  
(2, 4, 6)  
3
Read Cycle No. 2  
t
RC  
ADDR  
t
AA  
t
ACE  
CE1  
CE2  
5
t
t
HZCE  
LZCE  
OE  
6
t
t
HZOE  
LZOE  
D
OUT  
DATA VALID  
t
AOE  
7
AC Electrical Characteristics  
8
(7)  
(7)  
Description  
-10  
-12  
-15  
READ Cycle  
Sym  
Min. Max. Min. Max. Min. Max. Units  
9
READ cycle time  
t
10  
12  
15  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RC  
Address access time  
t
10  
10  
12  
12  
15  
15  
AA  
Chip enable access time  
Output hold from address change  
t
ACE  
t
3
5
3
5
3
5
10  
11  
12  
OH  
(1,3)  
Chip enable to output in low Z  
t
LZCE  
HZCE  
(1,2,3)  
Chip disable to output in high Z  
t
6
6
7
(3)  
Chip enable to power up time  
t
t
0
0
0
0
0
0
PU  
PD  
(3)  
Chip disable to power down time  
Output enable access time  
10  
6
12  
6
15  
6
t
AOE  
LZOE  
HZOE  
(1,3)  
(1,3)  
Output enable to output in low Z  
t
Output disable to output in high Z  
t
6
6
6
SHADED AREA = PRELIMINARY DATA  
Notes referenced are after Data Retention Table.  
Rev. 3.3 - 4/09/98  
5

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