PCA9605D

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PCA9605D 数据手册

PCA9605

Simple 2-wire bus buffer

Rev. 1 — 28 February 2011

Product data sheet

1. General description

The PCA9605 is a monolithic CMOS integrated circuit for bus buffering in applications

including I²C-bus, SMBus, DDC, PMBus, and other systems based on similar principles.

The buffer extends the bus load limit by buffering both the SCL and SDA lines, allowing

the maximum permissible bus capacitance on both sides of the buffer.

The PCA9605 includes a unidirectional buffer for the clock signal, and a bidirectional

buffer for the data signal. Slave devices which employ clock stretching are therefore not

supported.

In its most basic implementation, the buffer will allow an extended number of slave

devices to be attached to one (or more) master devices. In this case, all master devices

would be positioned on the Sxx_IN side of the PCA9605.

The direction pin (DIR) further enhances this function by allowing the unidirectional clock

signal to be reversed, thus allowing master devices on both sides of the buffer.

The enable (EN) function allows sections of the bus to be isolated. Individual parts of the

system can be brought on-line successively. This means a controlled start-up using a

diverse range of components, operating speeds and loads is easily achieved.

2. Features and benefits

 Simple impedance isolating buffer for 2-wire buses

 30 mA maximum static open-drain pull-down capability supports a wide range of bus

standards

 Works with I²C-bus (Standard-mode, Fast-mode, Fast-mode Plus), SMBus (standard

and high power mode), and PMBus

 Fast switching times allow operation in excess of 1 MHz

 Enable allows bus segments to be disconnected

 Hysteresis on inputs provides noise immunity

 Operating voltages from 2.7 V to 5.5 V

 Very low supply current

 Uncomplicated characteristics suitable for quick implementation in most common

2-wire bus applications

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